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Providing bus resiliency in a hybrid memory system

  • US 9,152,584 B2
  • Filed: 10/29/2013
  • Issued: 10/06/2015
  • Est. Priority Date: 10/29/2013
  • Status: Active Grant
First Claim
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1. A hybrid memory system for providing bus resiliency, the hybrid memory system comprising:

  • a host memory controller;

    a non-volatile memory DIMM (Dual Inline Memory Module); and

    a memory bus coupling the host memory controller to the DIMM, wherein;

    the DIMM is coupled to the host memory controller and comprises non-volatile memory, a DIMM bus adapter, and a local memory controller;

    the local memory controller is configured to control memory accesses within the DIMM; and

    the DIMM bus adapter is configured to;

    adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol;

    discover a memory error in the DIMM; and

    provide, to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and

    the host memory controller is further configured to perform one or more resiliency measures responsive to the indication of the error.

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