Device having data storage

• US 9,152,909 B2
• Filed: 12/04/2013
• Issued: 10/06/2015
• Est. Priority Date: 07/21/2008
• Status: Active Grant

• Current Assignee: SATO Holdings Corporation
• Original Assignee: SATO Vicinity Pty Limited (SATO Holdings Corporation)
• Inventors: Littlechild, Stuart Colin, Clarke, Robert John, Forsey, Gary Michael
• Primary Examiner(s): VO, TUYEN KIM
• Application Number:
  US14/096,882
• Publication Number:
  US 20140319226A1
• Time in Patent Office: 671 Days
• Field of Search: 235/375, 235/451, 235/492, 235/380
• US Class Current: 1/1
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H02H 7/20 for electronic equipment for converters H02H7/10; for electric measuring instruments G01R1/36; for dc voltage or current semiconductor regulators G05F1/569; for amplifiers H03F1/52; for electronic switching circuits H03K17/08

Abstract

Devices which store data for a period of time. In one form, devices store data in which the data store is subject to periodic and/or relatively short power outages. In one example, a radio frequency identification (“RFID”) transponder, and more particularly, a RFID transponder that is used in orientation independent applications, is disclosed. Other applications are directed to devices used where a supply power is intermittent. In a first aspect of embodiments described herein, there is disclosed a method of and/or device that includes a memory adapted to store data, a supply of power adapted to provide supply power to the memory, a path of leakage, the leakage path serving, over time, to diminish the integrity of data stored in the memory, and a leakage attenuator adapted to selectively attenuate the rate of leakage.

Claims

1. A device comprising:

a memory adapted to store data;

a supply of power adapted to provide supply power to the memory;

a leakage path, the leakage path serving, over time, to diminish integrity of data stored in the memory; and

a leakage attenuator comprising a plurality of serially coupled switches and adapted to control attenuation of a rate of leakage due to the leakage path when the supply of power has been removed from the device.

2. The device as claimed in claim 1, wherein the leakage attenuator is adapted to enable selection of a degree of attenuation of the rate of leakage.

3. The device as claimed in claim 1, wherein the leakage attenuator comprises a multistage switch.

4. The device as claimed in claim 3, wherein the multistage switch comprises a MOSFET.

5. The device as claimed in claim 1, wherein the leakage attenuator serves to perform at least one of reduce, attenuate control leakage associated with the memory.

6. The device as claimed in claim 1, wherein the memory comprises a memory cell.

7. The device as claimed in claim 1, wherein the leakage is sub-threshold leakage.

8. The device as claimed in claim 1, wherein the device is a transponder.

9. The device as claimed in claim 8, wherein the device is an RFID transponder.

10. The device as claimed in claim 1, wherein the time is less than 10 minutes.

11. The device as claimed in claim 1, wherein the time is less than 1 minute.

12. The device as claimed in claim 1, wherein the time is less than 1 second.

13. The device as claimed in claim 12, wherein the time is more than 50 msec.

14. A method of controlling leakage in a device comprising:

a memory adapted to store data;

a supply of power adapted to provide supply power to the memory;

a leakage path, the leakage path serving, over time, to diminish integrity of data stored in the memory, the method comprising;

providing a leakage attenuator adapted to control a rate of leakage due to the leakage path, the leakage attenuator being associated with the leakage path; and

wherein the leakage attenuator comprises a plurality of serially coupled switches and controls attenuation of the rate of leakage when the supply of power has been removed from the device.

15. The method as claimed in claim 14, where the leakage attenuator reduces sub-threshold leakage.

16. The method as claimed in claim 14, further comprising the step of providing a multistage switch as the leakage control device.

17. The method as claimed in claim 14, wherein the leakage attenuator is a plurality of switches.

18. The method as claimed in claim 14, wherein the leakage attenuator applies threshold adjustment.

19. The method as claimed in claim 14, further comprising controlling the leakage in a manner which enables data stored in the memory to remain valid for a period of time longer than an outage of power associated with the memory.

20. The method as claimed in claim 14, further comprising applying the method to a transponder.

21. The method of claim 20, wherein the transponder is selected from the group consisting of an RFID transponder and a passive device.

22. An apparatus adapted to controlling leakage in a device, said apparatus including:

processor means adapted to operate in accordance with a predetermined instruction set; and

said apparatus, in conjunction with said instruction set, being adapted to perform the method as claimed in claim 14.

23. The method as claimed in claim 14, wherein the time is less than 10 minutes.

24. The method as claimed in claim 14, wherein the device is an RFID transponder.

25. The method as claimed in claim 14, wherein the time is less than 1 minute.

26. The method as claimed in claim 14, wherein the time is less than 1 second.

27. The method as claimed in claim 26, wherein the time is more than 50 msec.