Apparatus for reducing write minimum supply voltage for memory

• US 9,153,304 B2
• Filed: 06/28/2012
• Issued: 10/06/2015
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kulkarni, Jaydeep P., Khellah, Muhammad M., Tschanz, James W., Geuskens, Bibiche M., De, Vivek K.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Bashar, Mohammed A
• Application Number:
  US13/536,521
• Publication Number:
  US 20140003132A1
• Time in Patent Office: 1,195 Days
• Field of Search: 365/154, 365/226, 365/230.05, 365/203
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Claims

1. An apparatus comprising:

a memory element having cross-coupled inverters coupled to a first supply node;

a power device coupled to the first supply node and a second supply node, the second supply node coupled to a power supply;

a first access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a first bit-line which is operable to be pre-discharged to a logical low level prior to write operation; and

a second access device having a gate terminal coupled to the word-line, a first terminal coupled to the memory element, and a second terminal coupled to a second bit-line which is operable to be pre-discharged to a logical low level prior to the write operation, wherein the first and second bit-lines are differential bit-lines, and wherein both the first and second bit-lines are operable to be pre-discharged to a logical low level prior to the write operation such that the power supply on the first supply node exhibits self-induced reduction.

2. The apparatus of claim 1 further comprises logic to pre-discharge the first bit-line prior to the write operation.

3. The apparatus of claim 2, wherein the logic is operable to pre-discharge the first bit-line during a memory inactive state.

4. The apparatus of claim 1 further comprises a delay logic operable to delay assertion or de-assertion of the first bit-line relative to the word-line.

5. The apparatus of claim 1, wherein the power device comprises a p-type device.

6. The apparatus of claim 1, wherein the power device comprises a stack of p-type devices coupled together in series between the first supply node and the second supply node.

7. The apparatus of claim 1, wherein the power device has a programmable resistance between the first power supply node and the second power supply node.

8. The apparatus of claim 1, wherein the power device is operable to receive a pulse signal to turn off the power device when the first bit-line is pre-discharged to the logical low level during the write operation.

9. The apparatus of claim 1, wherein the power device is operable to be turned on after the first bit-line transitions to a logical high level during the write operation.

10. The apparatus of claim 1, wherein the memory element and the first and second access devices are part of a 6T Static Random Access Memory (SRAM) cell or part of an 8T SRAM cell.

11. The apparatus of claim 1, wherein during normal operation, the second bit-line provides a signal which is an inverse of a signal provided by the first bit-line.

12. The apparatus of claim 1, wherein the cross-coupled inverters comprise corresponding p-type devices with first terminals coupled to the first supply node and second terminals coupled to at least one of the first or second access devices.

31. The apparatus of claim 4, wherein the delay between the first bit-line and word-line is programmable.

32. The apparatus of claim 4, wherein the delay unit is operable to set the delay between the first bit-line and the word-line in a range of 20% to 30% of a write clock phase.

33. The apparatus of claim 4, wherein the delay unit comprises a multiplexer which is operable to select an inverting path over a non-inverting path.

13. An apparatus comprising:

a power device having a p-type transistor operable to supply power supply to a first supply node; and

an Static Random Access Memory (SRAM) coupled to the first supply node, the SRAM having at least two access devices having their corresponding gate terminals coupled to a word-line, the at least two access devices having their corresponding first terminals coupled to cross-coupled inverters of the SRAM, and the at least two access devices having their corresponding second terminals coupled to complementary bit-lines which are operable to be pre-discharged to a logical low level prior to write operation, wherein both bit-lines of the complementary bit-lines are operable to be pre-discharged to a logical low level prior to the write operation such that the power supply on the first supply node exhibits self-induced reduction.

14. The apparatus of claim 13 further comprises logic to pre-discharge the complementary bit-lines prior to the write operation.

15. The apparatus of claim 14, wherein the logic is operable to pre-discharge the complementary bit-lines during a memory inactive state.

16. The apparatus of claim 13, wherein the SRAM is a 6T SRAM or an 8T SRAM.

17. The apparatus of claim 13, wherein during normal operation, the complementary bit-lines provide complementary signals.

18. The apparatus of claim 13, wherein the power device is operable to receive a pulse signal to turn off the power device when the complementary bit-lines are pre-discharged to the logical low level during the write operation.

19. The apparatus of claim 13, wherein the power device is operable to turn on after the complementary bit-lines transition to a logical high level during the write operation.

20. The apparatus of claim 13 further comprises delay logic operable to delay assertion or de-assertion of the complementary bit-lines relative to the word-line.

21. A system comprising:

a processor having memory comprising;

a memory element having cross-coupled inverters coupled to a first supply node;

a power device coupled to the first supply node and a second supply node, the second supply node coupled to a power supply;

a first access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a first bit-line which is operable to be pre-discharged to a logical low level prior to write operation; and

a second access device having a gate terminal coupled to the word-line, a first terminal coupled to the memory element, and a second terminal coupled to a second bit-line which is operable to be pre-discharged to a logical low level prior to the write operation, wherein the first and second bit-lines are differential bit-lines, and wherein both the first and second bit-lines are operable to be pre-discharged to a logical low level prior to the write operation such that the power supply on the first supply node exhibits self-induced reduction; and

a wireless interface communicatively coupled to the processor to allow the processor to communicate with other devices.

22. The system of claim 21 further comprises a display unit communicatively coupled to the processor.

23. The system of claim 21, wherein the processor further comprises logic to pre-discharge the first and second bit-lines prior to the write operation.

24. The system of claim 23, wherein the logic is operable to pre-discharge the first and second bit-lines during a memory inactive state.

25. The system of claim 21, wherein the processor further comprises a delay logic operable to delay assertion or de-assertion of the first bit-line relative to the word-line.

26. A system comprising:

a processor having a memory comprising;

a power device having a p-type transistor to supply power supply to a first supply node; and

an Static Random Access Memory (SRAM) coupled to the first supply node, the SRAM having at least two access devices having their corresponding gate terminals coupled to a word-line, the at least two access devices having their corresponding first terminals coupled to cross-coupled inverters of the SRAM, and the at least two access devices having their corresponding second terminals coupled to complementary bit-lines which are operable to be pre-discharged to a logical low level prior to write operation, wherein both bit-lines of the complementary bit-lines are operable to be pre-discharged to a logical low level prior to the write operation such that the power supply on the first supply node exhibits self-induced reduction; and

a wireless interface communicatively coupled to the processor to allow the processor to communicate with other devices.

27. The system of claim 26, wherein the processor further comprises logic to pre-discharge the complementary bit-lines prior to the write operation.

28. The system of claim 27, wherein the logic is operable to pre-discharge the complementary bit-lines during a memory inactive state.

29. The system of claim 28, wherein the SRAM is a 6T SRAM or an 8T SRAM.

30. The system of claim 26 further comprises a display unit communicatively coupled to the processor.