Semiconductor memory device having electrically floating body transistor, semiconductor memory device having both volatile and non-volatile functionality and method or operating
First Claim
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1. A semiconductor memory cell comprising:
- a substrate;
a floating body region configured to store volatile memory;
a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; and
a select gate positioned adjacent said substrate and said floating gate.
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
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8 Claims
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1. A semiconductor memory cell comprising:
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a substrate; a floating body region configured to store volatile memory; a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; and a select gate positioned adjacent said substrate and said floating gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification