System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers

• US 9,153,311 B1
• Filed: 05/27/2014
• Issued: 10/06/2015
• Est. Priority Date: 05/27/2014
• Status: Expired due to Fees

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, LLC
• Inventors: Tewalt, Timothy J.
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/288,094
• Time in Patent Office: 497 Days
• Field of Search: 365/222
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs

Abstract

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with an internally or externally located data maintenance block wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

Claims

1. A computer system comprising:

a DRAM memory;

a reconfigurable logic device having a memory controller coupled to selected inputs and outputs of said DRAM memory; and

a data maintenance block coupled to said reconfigurable logic device and self-refresh command inputs of said DRAM memory, said data maintenance block operative to provide stable input levels on said self-refresh command inputs while said reconfigurable logic device is reconfigured.

2. The computer system of claim 1 wherein said DRAM memory comprises DDR3 compliant memory devices.

3. The computer system of claim 1 wherein said reconfigurable logic device comprises an FPGA.

4. The computer system of claim 1 wherein said data maintenance block comprises a command decode portion coupled to a reconfigure controller of said reconfigurable logic device.

5. The computer system of claim 4 wherein said command decode portion of said data maintenance block is operative in response to a command from said reconfigure controller and provides an acknowledgement signal in response.

6. The computer system of claim 1 wherein said data maintenance block comprises a memory block coupled to a reconfigure controller of said reconfigurable logic device.

7. The computer system of claim 6 wherein said memory block is operative to retain data received from said reconfigure controller of said reconfigurable logic device.

8. The computer system of claim 1 wherein said data maintenance block comprises a CPLD.

9. The computer system of claim 1 wherein said reconfigurable logic device comprises said data maintenance block.

10. The computer system of claim 1 wherein said data maintenance block is operable to hold said DRAM memory in self-refresh mode while said reconfigurable logic device is reconfigured.

11. A method for preserving contents of a DRAM memory associated with a reconfigurable device having a memory controller comprising:

providing a data maintenance block coupled to said reconfigurable device;

coupling said data maintenance block to self-refresh command inputs of said DRAM memory;

storing data received from said reconfigurable device at said data maintenance block; and

maintaining stable input levels on said self-refresh command inputs while said reconfigurable logic device is reconfigured.

12. The method of claim 11 wherein said step of providing comprises:

providing a command decode portion of said data maintenance block coupled to receive commands from said reconfigurable device and return acknowledgment signals in response thereto.

13. The method of claim 11 wherein said step of storing comprises:

providing a memory block in said data maintenance block for storing said data received from said reconfigurable device and returning said data to said reconfigurable device upon completion of a reconfiguration function.

14. The method of claim 11 wherein said step of storing comprises:

providing a memory block in said data maintenance block for storing said data received directly from said DRAM memory and returning said data directly to said DRAM memory upon completion of a reconfiguration function.

15. The method of claim 11 wherein said step of providing said data maintenance block comprises:

providing a portion of said reconfigurable device as said data maintenance block.

16. The method of claim 11 wherein said step of providing said data maintenance block comprises:

providing a CPLD as said data maintenance block.

17. The method of claim 11 wherein said step of providing said data maintenance block comprises:

providing a block RAM for storing said data received from said reconfigurable device; and

providing a command decode portion responsive to said reconfigurable device and coupled to said reset and lock enable inputs of said DRAM memory.

18. The method of claim 11 further comprising:

passing said data between sequential computing tasks in a reconfigurable computing environment.

19. The method of claim 11 further comprising:

preserving said data at said data maintenance block while said reconfigurable logic device is powered down.