Flash memory apparatus with voltage boost circuit

• US 9,153,327 B2
• Filed: 02/14/2014
• Issued: 10/06/2015
• Est. Priority Date: 08/01/2011
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Ching, Wen-Hao, Wang, Shih-Chen
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US14/180,373
• Publication Number:
  US 20140160859A1
• Time in Patent Office: 599 Days
• Field of Search: 365/185.25, 365/185.18, 365/185.28, 365/182
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits

Abstract

A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.

Claims

1. A flash memory apparatus, comprising:

a plurality of memory cell regions, wherein each of the memory cell regions comprises;

a plurality of memory cells, wherein each of the memory cells receives a programming control voltage through a control end point, and receives an erasing control voltage through an erase end point;

a programming control voltage generator, coupled to the memory cells, wherein the programming control voltage generator comprises;

a pre-charge voltage transmitter, coupled to all the control end points of the memory cells, providing a pre-charge voltage to the control end point of the memory cells according to a pre-charge enable signal during a first period of time; and

a pumping capacitor, coupled between the control end point of the memory cells and a pumping voltage which is applied to the pumping capacitor during a second period of time, generating the programming control voltage at the control end point of the memory cells; and

an erasing control voltage generator, coupled to the memory cells, wherein the erasing control voltage generator comprises;

an erasing pre-charge voltage transmitter, coupled to all the erase end points of the memory cells, providing an erasing pre-charge voltage to the erase end point of the memory cells according to an erasing pre-charge enable signal during a third period of time; and

an erasing pumping capacitor, coupled between the erase end point of the memory cells and an erasing pumping voltage which is applied to the erasing pumping capacitor during a fourth period of time, generating the erasing control voltage for erasing.

2. The flash memory apparatus as claimed in claim 1, wherein the pre-charge voltage transmitter comprises:

a pre-charge programming switch, coupled between the pre-charge voltage and the control end points of the memory cells, the pre-charge programming switch is turned on for transmitting the pre-charge voltage to the control end point according to the pre-charge enable signal.

3. The flash memory apparatus as claimed in claim 2, wherein the pre-charge programming switch comprises:

a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor respectively coupled to the control end point of the corresponding memory cell and the pre-charge voltage, and the control end of the first transistor receiving the pre-charge enable signal.

4. The flash memory apparatus as claimed in claim 3, wherein the pre-charge programming switch further comprises:

a second transistor, coupled on the path where the first transistor coupled to the control end point of the corresponding memory cell, having a first end, a second end, and a control end, wherein the first end of the second transistor coupled to the control end point of the corresponding memory cell, the second end of the second transistor coupled to the first end of the first transistor, and the control end of the second transistor receiving a control signal.

5. The flash memory apparatus as claimed in claim 1, wherein the pre-charge voltage transmitter comprises:

a first pre-charge programming switch, coupled between a first pre-charge voltage and the control end point of the corresponding memory cell; and

a second pre-charge programming switch, coupled between a second pre-charge voltage and the control end point of the corresponding memory cell,

wherein the first pre-charge programming switch and the second pre-charge programming switch are respectively controlled by a first pre-charge enable signal and a second pre-charge enable signal, and the first pre-charge programming switch transmitting the first pre-charge voltage to the control end point of the corresponding memory cell or the second pre-charge programming switch transmitting the second pre-charge voltage to the control end point of the corresponding memory cell.

6. The flash memory apparatus as claimed in claim 5, wherein the first pre-charge programming switch comprises:

a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor respectively coupled to the control end point of the corresponding memory cell and the first pre-charge voltage, and the control end of the first transistor receiving the first pre-charge enable signal; and

the second pre-charge programming switch comprises;

a second transistor having a first end, a second end and a control end, wherein the first end and the second end respectively coupled to the control end point of the corresponding memory cell and the second pre-charge voltage, and the control end of the second transistor receiving the second pre-charge enable signal.

7. The flash memory apparatus as claimed in claim 6, wherein the first pre-charge programming switch further comprises:

a third transistor, coupled on the path where the first transistor coupled to the control end point of the corresponding memory cell, having a first end, a second end, and a control end, wherein the first end of the third transistor coupled to the control end point of the corresponding memory cell, the second end of the third transistor coupled to the first end of the first transistor, and the control end of the third transistor receiving a first control signal; and

the second pre-charge programming switch further comprises;

a fourth transistor, coupled on the path where the second transistor coupled to the control end point of the corresponding memory cell, having a first end, a second end, and a control end, wherein the first end of the fourth transistor coupled to the control end point of the corresponding memory cell, the second end of the fourth transistor coupled to the first end of the second transistor, and the control end of the fourth transistor receiving a second control signal.

8. The flash memory apparatus as claimed in claim 7, wherein the second transistor and the fourth transistor are P-type transistors, and the first transistor and the third transistor are N-type transistors.

9. The flash memory apparatus as claimed in claim 1, wherein each of the memory cells comprises:

a floating-gate transistor.

10. The memory cell as claimed in claim 9, wherein the floating-gate transistor is fabricated by:

a single-poly CMOS process.

11. The flash memory apparatus as claimed in claim 1, wherein the memory cell comprises:

a dielectric storage transistor.

12. The flash memory apparatus as claimed in claim 1, wherein each of the memory cells coupled to a source line and a bit line comprises:

a storage transistor, having a first end, a second end, and a control end, wherein the first end of the storage transistor coupled to the source line, and the second end of the storage transistor coupled to the bit line;

a selecting transistor, coupled on the path where the source line coupled to the storage transistor, having a first end, a second end, and a control end, wherein the first end of the selecting transistor coupled to the source line, the second end of the selecting transistor coupled to first end of the storage transistor, and the control end of the selecting transistor receiving a selecting signal;

an operation transistor, coupled on the path where the bit line coupled to the storage transistor, having a first end, a second end, and a control end, wherein the first end of the operation transistor coupled to the second end of the storage transistor, the second end of the operation transistor coupled to the bit line, and the control end of the operation transistor receiving a word line enable signal; and

a gate capacitor, coupled between the programming control voltage and the control end of the storage transistor; and

an erase gate capacitor, coupled between an erase control voltage and an erase end point of the storage transistor.

13. The memory cell as claimed in claim 12, wherein the storage transistor is:

a floating-gate transistor.

14. The flash memory apparatus as claimed in claim 1, wherein the erasing pre-charge voltage transmitter comprises:

an erasing pre-charge switch, coupled between the erasing pre-charge voltage and an erase end point of the corresponding memory cell, which is turned on according to the erasing pre-charge enable signal for transmitting the erasing pre-charge voltage to the erase end point.

15. The flash memory apparatus as claimed in claim 14, wherein the erasing pre-charge switch comprises:

a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor respectively coupled to the erase end point of the corresponding memory cell and the erasing pre-charge voltage, and the control end of the first transistor receiving the erasing pre-charge enable signal.

16. The flash memory apparatus as claimed in claim 15, wherein the erasing pre-charge switch further comprises:

a second transistor, coupled on the path where the first transistor coupled to the erase end point of the corresponding memory cell, having a first end, a second end, and a control end, wherein the first end of the second transistor coupled to the erase end point of the corresponding memory cell, the second end of the second transistor coupled to the first end of the first transistor, and the control end of the second transistor receiving a control signal.

17. The flash memory apparatus as claimed in claim 1, wherein the erasing pre-charge voltage transmitter comprises:

a first erasing pre-charge switch, coupled between a first erasing pre-charge voltage and the erase end point of the corresponding memory cell; and

a second erasing pre-charge switch, coupled between a second erasing pre-charge voltage and the erase end point of the corresponding memory cell,

wherein the first erasing pre-charge switch and the second erasing pre-charge switch are respectively controlled by a first erasing pre-charge enable signal and a second erasing pre-charge enable signal, and transmitting the first erasing pre-charge voltage or the second erasing pre-charge voltage to the erase end point of the corresponding memory cell.

18. The flash memory apparatus as claimed in claim 17, wherein the first erasing pre-charge switch comprises:

a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor respectively coupled to the erase end point of the corresponding memory cell and the first erasing pre-charge voltage, and the control end of the first transistor receiving the first erasing pre-charge enable signal; and

the second erasing pre-charge switch comprises;

a second transistor having a first end, a second end, and a control end, wherein the first end and the second end of the second transistor respectively coupled to the erase end point of the corresponding memory cell and the second erasing pre-charge voltage, and the control end of the second transistor receiving the second erasing pre-charge enable signal.

19. The flash memory apparatus as claimed in claim 18, wherein the first erasing pre-charge switch further comprises:

a third transistor, coupled on the path where the first transistor coupled to the erase end point of the corresponding memory cell, having a first end, a second end, and a control end, wherein the first end of the third transistor coupled to the erase end point of the corresponding memory cell, the second end of the third transistor coupled to the first end of the first transistor, and the control end of the third transistor receiving a first erasing control signal; and

the second erasing pre-charge switch further comprises;

a fourth transistor, coupled on the path where the second transistor coupled to the erase end point of the corresponding memory cell, having a first end, a second end, and a control end, wherein the first end of the fourth transistor coupled to the erase end point of the corresponding memory cell, the second end of the fourth transistor coupled to the first end of the second transistor, and the control end of the fourth transistor receiving a second erasing control signal.

20. The flash memory apparatus as claimed in claim 19, wherein the second transistor and the fourth transistor are P-type transistors, and the first transistor and the third transistor are N-type transistors.

21. The flash memory apparatus as claimed in claim 1, wherein the third period of time is overlapped with at least one of the first and second periods of time, and the fourth period of time is overlapped with at least one of the first and second periods of time.

22. A flash memory apparatus, comprising:

a plurality of memory cell regions, wherein each of the memory cell regions comprises;

a plurality of memory cells, wherein each of the memory cells receives a programming control voltage through a control end point, and receives an erasing control voltage through an erase end point;

a plurality of programming control voltage generators, respectively coupled to the memory cells, wherein the each of the programming control voltage generator comprises;

a pre-charge voltage transmitter, coupled to the control end point of the corresponding memory cell, providing a pre-charge voltage to the control end point of the corresponding memory cell according to a pre-charge enable signal during a first period of time; and

a pumping capacitor, coupled between the control end point of the corresponding memory cell and a pumping voltage which is applied to the pumping capacitor during a second period of time, generating the programming control voltage at the control end point of the corresponding memory cell; and

an erasing control voltage generator, coupled to the memory cells, wherein the erasing control voltage generator comprises;

an erasing pre-charge voltage transmitter, coupled to all the erase end point of memory cells, providing an erasing pre-charge voltage to the erase end point of the memory cells according to an erasing pre-charge enable signal during a third period of time; and

an erasing pumping capacitor, coupled between the erase end point of the memory cells and an erasing pumping voltage which is applied to the erasing pumping capacitor during a fourth period of time, generating the erasing control voltage for erasing.