Flash memory apparatus with voltage boost circuit
First Claim
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1. A flash memory apparatus, comprising:
- a plurality of memory cell regions, wherein each of the memory cell regions comprises;
a plurality of memory cells, wherein each of the memory cells receives a programming control voltage through a control end point, and receives an erasing control voltage through an erase end point;
a programming control voltage generator, coupled to the memory cells, wherein the programming control voltage generator comprises;
a pre-charge voltage transmitter, coupled to all the control end points of the memory cells, providing a pre-charge voltage to the control end point of the memory cells according to a pre-charge enable signal during a first period of time; and
a pumping capacitor, coupled between the control end point of the memory cells and a pumping voltage which is applied to the pumping capacitor during a second period of time, generating the programming control voltage at the control end point of the memory cells; and
an erasing control voltage generator, coupled to the memory cells, wherein the erasing control voltage generator comprises;
an erasing pre-charge voltage transmitter, coupled to all the erase end points of the memory cells, providing an erasing pre-charge voltage to the erase end point of the memory cells according to an erasing pre-charge enable signal during a third period of time; and
an erasing pumping capacitor, coupled between the erase end point of the memory cells and an erasing pumping voltage which is applied to the erasing pumping capacitor during a fourth period of time, generating the erasing control voltage for erasing.
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Abstract
A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.
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Citations
22 Claims
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1. A flash memory apparatus, comprising:
a plurality of memory cell regions, wherein each of the memory cell regions comprises; a plurality of memory cells, wherein each of the memory cells receives a programming control voltage through a control end point, and receives an erasing control voltage through an erase end point; a programming control voltage generator, coupled to the memory cells, wherein the programming control voltage generator comprises; a pre-charge voltage transmitter, coupled to all the control end points of the memory cells, providing a pre-charge voltage to the control end point of the memory cells according to a pre-charge enable signal during a first period of time; and a pumping capacitor, coupled between the control end point of the memory cells and a pumping voltage which is applied to the pumping capacitor during a second period of time, generating the programming control voltage at the control end point of the memory cells; and an erasing control voltage generator, coupled to the memory cells, wherein the erasing control voltage generator comprises; an erasing pre-charge voltage transmitter, coupled to all the erase end points of the memory cells, providing an erasing pre-charge voltage to the erase end point of the memory cells according to an erasing pre-charge enable signal during a third period of time; and an erasing pumping capacitor, coupled between the erase end point of the memory cells and an erasing pumping voltage which is applied to the erasing pumping capacitor during a fourth period of time, generating the erasing control voltage for erasing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A flash memory apparatus, comprising:
a plurality of memory cell regions, wherein each of the memory cell regions comprises; a plurality of memory cells, wherein each of the memory cells receives a programming control voltage through a control end point, and receives an erasing control voltage through an erase end point; a plurality of programming control voltage generators, respectively coupled to the memory cells, wherein the each of the programming control voltage generator comprises; a pre-charge voltage transmitter, coupled to the control end point of the corresponding memory cell, providing a pre-charge voltage to the control end point of the corresponding memory cell according to a pre-charge enable signal during a first period of time; and a pumping capacitor, coupled between the control end point of the corresponding memory cell and a pumping voltage which is applied to the pumping capacitor during a second period of time, generating the programming control voltage at the control end point of the corresponding memory cell; and an erasing control voltage generator, coupled to the memory cells, wherein the erasing control voltage generator comprises; an erasing pre-charge voltage transmitter, coupled to all the erase end point of memory cells, providing an erasing pre-charge voltage to the erase end point of the memory cells according to an erasing pre-charge enable signal during a third period of time; and an erasing pumping capacitor, coupled between the erase end point of the memory cells and an erasing pumping voltage which is applied to the erasing pumping capacitor during a fourth period of time, generating the erasing control voltage for erasing.
Specification