Methods of forming semiconductor device structures, memory cells, and arrays
First Claim
1. A method of forming a semiconductor device structure, the method comprising:
- forming a liner on a conductive material on a base material;
exposing the liner to a radical oxidation treatment to form a densified liner on the conductive material; and
patterning the base material while protecting the conductive material from patterning with the densified liner.
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Accused Products
Abstract
Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
25 Citations
21 Claims
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1. A method of forming a semiconductor device structure, the method comprising:
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forming a liner on a conductive material on a base material; exposing the liner to a radical oxidation treatment to form a densified liner on the conductive material; and patterning the base material while protecting the conductive material from patterning with the densified liner. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a memory cell, the method comprising:
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forming a control gate region over a dielectric material; substantially conformally forming a liner on at least sidewalk of the control gate region; exposing the liner to oxygen radicals, hydrogen radicals, and heat to form a densified liner, on at least the sidewalk of the control gate region, having a thickness not greater than a thickness of the liner before exposing the liner to the oxygen radicals, the hydrogen radicals, and the heat; and selectively removing portions of the dielectric material using the densified liner to protect the sidewalk of the control gate region from exposure. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of forming an array of memory cells, the method comprising:
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forming features comprising at least one conductive material on a dielectric material exposed between the features; forming an oxide liner on sidewalk of the features and on the dielectric material; exposing the oxide liner to an in situ steam generation (ISSG) process to form a densified oxide liner on the sidewalls of the features; and removing a portion of the dielectric material and another conductive material beneath the dielectric material while preventing exposure of the at least one conductive material with the densified oxide liner. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification