Solid-state imaging device, manufacturing method of solid-state imaging device, manufacturing method of semiconductor device, semiconductor device, and electronic device

• US 9,153,490 B2
• Filed: 07/12/2012
• Issued: 10/06/2015
• Est. Priority Date: 07/19/2011
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Mitsuhashi, Ikue, Akiyama, Kentaro, Kikuchi, Koji
• Primary Examiner(s): Legasse, Jr., Francis M
• Application Number:
  US13/547,698
• Publication Number:
  US 20130020468A1
• Time in Patent Office: 1,181 Days
• Field of Search: 257/431, 257/432, 257/433, 257/434, 250/208.1, 250/208.2, 250/214.1, 250/214.R, 250/214.DC
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A solid-state imaging device has a sensor substrate having a pixel region on which photoelectric converters are arrayed; a driving circuit provided on a front face side that is opposite from a light receiving face as to the photoelectric converters on the sensor substrate; an insulation layer, provided on the light receiving face, and having a stepped construction wherein the film thickness of the pixel region is thinner than the film thickness in a periphery region provided on the outside of the pixel region; a wiring provided to the periphery region on the light receiving face side; and on-chip lenses provided to positions corresponding to the photoelectric converters on the insulation layer.

Claims

1. A manufacturing method of a semiconductor device, comprising:

forming a first circuit substrate on which a first wiring is provided;

forming a second circuit substrate on which a second wiring is provided;

facing said first circuit substrate to an upper face of said second circuit substrate, and layering and bonding thereto;

forming a first opening on an upper face of said first wiring on a layered body of said first circuit substrate and said second circuit substrate, and forming a second opening on an upper face of said second wiring, wherein said first opening extends along a first line through an entire thickness of said first circuit substrate, and a portion of a first wiring layer that includes the first wiring, and wherein said second opening extended along a second line through all of said first semiconductor substrate, an entire thickness of the first wiring layer that includes the first wiring, and a portion of a second wiring layer that includes the second wiring;

forming a connecting conductive layer by filling in a metallic material within said first opening and said second opening to provide a first plug and a second plug, wherein the first plug is in electrical contact with the first wiring, and wherein said second plug is in electrical contact with said second wiring, and wherein said first line is separate and spaced apart from said second line within a plane parallel to the upper face of said second circuit substrate, and to provide connective wiring to electrically connect said first plug and said second plug, wherein said connective wiring is formed adjacent a first surface of the first circuit substrate on a side of the first circuit substrate that is opposite said second circuit substrate, wherein said connective wiring extends along a third line that is perpendicular to the first and second lines and that is parallel to the first surface of the first circuit substrate, and wherein said first wiring is electrically connected to said second wiring through said first plug, said connecting conductive layer, and said second plug;

forming a passivation film so as to cover an upper face of said connective wiring in said connecting conductive layer;

wherein, in said forming of said passivation film, said passivation film is formed by forming an insulating film of one of SiO₂, SiOC, or SiOF, with a high-density plasma CVD method, O3 TEOS CVD method, or ALD method.

2. The manufacturing method of a semiconductor device of claim 1, further comprising:

forming an insulating film that covers at least a portion of the first connecting conductive layer and at least a portion of the first circuit substrate.

3. The manufacturing method of a semiconductor device of claim 1, wherein the at least one photodiode is formed in the first circuit substrate.

4. The manufacturing method of a semiconductor device of claim 2, wherein the passivation film covers at least a portion of the insulating film.

5. A semiconductor device comprising:

a layered body including a first circuit substrate on which a first wiring layer that includes a first wiring is provided is faced and bonded to an upper face of a second circuit substrate on which a second wiring layer that includes a second wiring is provided;

a connecting conductive layer that is provided on an upper face side of said layered body, and that electrically connects said first wiring and said second wiring; and

a passivation film provided on the upper face of said layered body so as to cover said connecting conductive layer;

said connecting conductive layer further including

a first plug and a second plug provided by filling a metallic material in a first opening formed on an upper face of said first wiring of the layered body of said first circuit substrate and said second circuit substrate, and in a second opening formed on an upper face of said second wiring thereof, wherein said first plug extends along a first line through an entire thickness of the first circuit substrate, and a portion of the first wiring layer to electrically contact the first wiring, wherein said second plug extends along a second line through all of the first semiconductor substrate, an entire thickness of the first wiring layer, and a portion of the second wiring layer to contact that second wiring, and wherein said third line is parallel to, separate from, and spaced apart from the second line in a plane parallel to the upper face side of the layered body; and

a connective wiring formed with a metallic material so as to electrically connect said first plug and said second plug, wherein the connective wiring extends along a third line that is perpendicular to the first and second lines and that is parallel to the upper face side of the layered body;

wherein said passivation film is formed by forming an insulating film of one of SiO₂, SiOC, or SiOF, with a high-density plasma CVD method, O3 TEOS CVD method, or ALD method.

6. The semiconductor device of claim 5, further comprising an insulating film, wherein the insulating film covers at least a portion of the connective wiring and at least a portion of the first circuit substrate.

7. The semiconductor device of claim 5, wherein the passivation film covers at least a portion of the insulating film.

8. The semiconductor device of claim 5, wherein the first substrate includes at least one photodiode.

9. An electronic device comprising:

a layered body including a first circuit substrate on which a first wiring layer that includes a first wiring is provided is faced and bonded to an upper face of a second circuit substrate on which a second wiring layer that includes a second wiring is provided;

a connecting conductive layer that is provided on an upper face side of said layered body, and that electrically connects said first wiring and said second wiring; and

a passivation film provided on the upper face of said layered body so as to cover said connecting conductive layer;

said connecting conductive layer further including

a first plug and a second plug provided by filling a metallic material in a first opening formed on an upper face of said first wiring of the layered body of said first circuit substrate and said second circuit substrate, and in a second opening formed on an upper face of said second wiring thereof, wherein said first plug extends along a first line through an entire thickness of the first circuit substrate, and a portion of the first wiring layer to electrically contact the first wiring, wherein said second plug extends along a second line through all of the first semiconductor substrate, an entire thickness of the first wiring layer, and a portion of the second wiring layer to contact the second wiring, and wherein said third line is parallel to, separate from, and spaced from the second line in a plane parallel to the upper face side of the layered body; and

a connective wiring formed with a metallic material so as to electrically connect said first plug and said second plug, wherein the connective wiring extends along a third line that is perpendicular to the first and second lines and that is parallel to the upper face side of the layered body;

wherein said passivation film is formed by forming an insulating film of one of SiO₂, SiOC, or SiOF, with a high-density plasma CVD method, O3 TEOS CVD method, or ALD method.

10. The electronic device of claim 9, further comprising an insulating film, wherein the insulating film covers at least a portion of the connective wiring and at least a portion of the first circuit substrate.

11. The electronic device of claim 9, wherein the passivation film covers at least a portion of the insulating film.

12. The electronic device of claim 9, wherein the first substrate includes at least one photodiode.