Fault tolerant design for large area nitride semiconductor devices

• US 9,153,509 B2
• Filed: 12/12/2014
• Issued: 10/06/2015
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Original Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Inventors: Tweddle, Howard, Springett, Nigel, Klowak, Gregory P., McKnight-MacNeil, Cameron, Mizan, Ahmad
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US14/568,507
• Publication Number:
  US 20150162252A1
• Time in Patent Office: 298 Days
• Field of Search: 257/231, 257/241, 257/341, 257/390, 257/401, 257618-620
• US Class Current: 1/1
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Claims

1. A nitride semiconductor device comprising:

a substrate;

a nitride semiconductor layer formed on a device area of the substrate, the nitride semiconductor layer defining a plurality of active regions for an array of islands of a multi-island transistor, the array of islands extending in first and second directions over the device area;

each of said active regions comprising a two dimensional electron gas (2DEG) region isolated from adjacent active regions by an intervening inactive region of the device area;

each island having a source electrode, a drain electrode and a gate electrode formed on a respective active region of the island, each source electrode having a plurality of source peninsulas, each drain electrode having a plurality of drain peninsulas, the source and drain peninsulas being interleaved and spaced apart over the active region of the island to define a channel region therebetween, the gate electrode being formed on the nitride semiconductor layer over the channel region and running between the source and drain peninsulas across the island;

each source electrode having a source contact area, each drain electrode having a drain contact area, each gate electrode having a gate contact area;

the source, drain and gate electrodes of each island of the array of islands being arranged so that each island is electrically isolated from the source, drain and gate electrodes of neighboring islands in at least one of said first and second directions;

an overlying interconnect structure comprising at least one dielectric isolation layer and at least one metallization layer;

the at least one dielectric isolation layer being patterned to provide contact openings only to source, drain and gate contact areas of non-defective islands, while electrically isolating contact areas of defective islands; and

the at least one metallization layer providing;

a source interconnection interconnecting in parallel the source electrodes of multiple islands;

a drain interconnection interconnecting in parallel the drain electrodes of multiple islands; and

a gate interconnection interconnecting the gate electrodes of multiple islands to form a common gate,

said overlying interconnect structure thereby selectively interconnecting non-defective islands of the multi-island transistor and providing electrical isolation of defective islands.

2. The nitride semiconductor device of claim 1 wherein the source, drain and gate electrode contact areas of individual islands each comprise a contact pad having at least a minimum size of 80 μ

m required for electrical probing and testing for identification of defective islands before formation of the overlying interconnect structure.

3. The nitride semiconductor device of claim 1 wherein the array of islands comprises a matrix of rows and columns of islands.

4. The nitride semiconductor device of claim 1 wherein the array comprises rows and columns of islands, and the source and drain electrodes of each island of the array are arranged such that:

in the first direction (row-wise), except at edges of the array, each source electrode is positioned adjacent to a source electrode of a neighboring island, and each drain electrode is adjacent to a drain electrode of a neighboring island, so as to provide isolation comprising an inactive region between neighboring islands in the first direction;

in the second direction (column-wise), except at edges of the array, at least some source electrodes are positioned adjacent a source electrode of a neighboring island, and at least some drain electrodes are positioned adjacent a drain electrode of a neighboring island, so as to provide isolation comprising an inactive region between sets of neighboring islands in the second direction; and

each source electrode contact area, each drain electrode contact area and each gate electrode contact area comprising a respective contact pad, each contact pad being located over the inactive region of the substrate extending between islands in the first direction.

5. The nitride semiconductor device of claim 4 wherein, in the second direction, except at edges of the array, each source electrode is positioned adjacent a source electrode of a neighboring island, and each drain electrode is positioned adjacent a drain electrode of a neighboring island, so as to provide isolation comprising an inactive region between each neighboring island in the second direction.

6. The nitride semiconductor device of claim 4 wherein, in the second direction, except at edges of the array, for a set of islands, a side of at least one source electrode is positioned adjacent a source electrode of a neighboring island, and/or a side of at least one drain electrode is positioned adjacent a drain electrode of a neighboring island, so as to provide isolation comprising an inactive region between sets of neighboring islands in the second direction.

7. The nitride semiconductor device of claim 4 wherein for each group of four islands, the source and drain electrodes are arranged to provide isolation between each row of islands.

8. The nitride semiconductor device of claim 4 wherein, the rows and columns of islands of the array are arranged as a repeating pattern of a group of four islands, wherein the source and drain electrodes are arranged to provide isolation between at least each row of islands.

9. The nitride semiconductor device of claim 4 wherein source electrodes of neighboring islands in the first (row-wise) and second (column-wise) directions are coupled to form a common source electrode for each neighboring pair of rows of islands.

10. The nitride semiconductor device of claim 9 wherein the source and drain electrodes are further arranged to provide an active region between each column of islands.

11. The nitride semiconductor device of claim 10 wherein source electrodes of adjacent islands in a row-wise direction are interconnected to form a common source across at least part of the row.

12. The nitride semiconductor device of claim 9 wherein, for a normally-on device, for each island, the contact area of the gate electrode is arranged over the inactive region in the vicinity of the source contact area of the respective island.

13. The nitride semiconductor device of claim 4 wherein said contact areas of the respective source electrodes and drain electrodes of each island are provided on promontories of each respective source and drain electrode, said promontories extending over the inactive region.

14. The nitride semiconductor device of claim 4 comprising a center-fed gate arrangement wherein gate contact areas of each neighboring island pair in a first direction comprise gate contact pads centered over the inactive region between each neighboring island pair and a gate connection connecting a center region of each island gate electrode to its respective gate contact pad.

15. The nitride semiconductor device of claim 4 wherein the array comprises a plurality of islands arranged as a repeating pattern of a building block of four islands.

16. The nitride semiconductor device of claim 4 wherein the array comprises a plurality of islands arranged as a repeating pattern of a building block of four islands, the four islands of the building block being arranged in a pattern having p2 mg symmetry.

17. The nitride semiconductor device of claim 1 wherein the gate interconnection comprises one or a plurality of gate straps extending in the first direction and interconnecting gate contact areas of adjacent islands;

the source interconnection comprises one or a plurality of source straps extending in the first direction and interconnecting source electrodes of adjacent islands; and

the drain interconnection comprises one or a plurality of drain straps extending in the first direction and interconnecting source electrodes of adjacent islands.

18. The nitride semiconductor device of claim 1 wherein the source, drain and gate interconnections further comprise a metallization layer defining large area source contact pads interconnecting each neighboring pair of source contacts, large area drain contact pads interconnecting each neighboring pair of drain contacts, large area gate contact pads interconnecting each neighboring pair of gate contact areas;

an insulating layer isolating the large area source, drain and gate contact pads from each other, and an overlying conductive layer defining source, drain and gate straps, and conductive vias extending through the insulating layer from the source, drain and gate straps to respective large area source, drain and gate contact pads.

19. The nitride semiconductor device of claim 1 wherein the nitride semiconductor layer comprises a gallium nitride/aluminum gallium nitride (GaN/AlGaN) heterostructure layer defining said 2DEG regions, and wherein said overlying interconnect structure interconnects source, drain and gate electrodes of each non-defective island of the array to form a large gate-width multi-island GaN HEMT (High Electron Mobility Transistor).

20. The nitride semiconductor device of claim 19 fabricated on a silicon or silicon carbide substrate, and further comprising at least one Metal Oxide Semiconductor Field Effect Transistor (MOSFET) driver chip mounted on the substrate adjacent to the GaN HEMT transistor, and directly interconnected thereto, in cascode configuration.

21. The nitride semiconductor device of claim 1, wherein the source, drain and gate contact areas of individual islands each comprise a contact pad having at least a minimum size of 25 μ

m required for electrical probing and testing for identification of defective islands before formation of the overlying interconnect structure.