Electrical connector between die pad and z-interconnect for stacked die assemblies

• US 9,153,517 B2
• Filed: 05/17/2011
• Issued: 10/06/2015
• Est. Priority Date: 05/20/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Co, Reynaldo, Leal, Jeffrey S., Pangrle, Suzette K., McGrath, Scott, Melcher, DeAnn Eileen, Barrie, Keith L., Villavicencio, Grant, del Rosario, Elmer M., Bray, John R.
• Primary Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US13/109,996
• Publication Number:
  US 20120119385A1
• Time in Patent Office: 1,603 Days
• Field of Search: 257/777, 257/E21.599, 257/E23.141, 438/460, 438/462, 438/113, 438/613, 438/465
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03318 by dispensing droplets
• CPC Class Codes: H01L 2224/0332 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/03632 Ablation by means of a laser or focused ion beam [FIB]
• CPC Class Codes: H01L 2224/03848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/05016 in side view
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/0529 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 : Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82102 : using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Claims

1. A method for forming a connector on a die pad at a wafer level of processing, comprising:

forming a conformal electrically insulative coating overlying at least a front surface of the wafer, wherein the die pads are exposed by openings in the conformal coating;

forming a channel defining an interconnect die edge and a void within the channel;

forming spots of a curable electrically conductive polymer material after forming the conformal electrically insulative coating, wherein the spots are formed over the die pad and extending over the interconnect die edge and at least partially over the void;

curing the conductive polymer material; and

in a wafer cutting procedure thereafter, severing the spots.

2. The method of claim 1, wherein the spots entirely bridge the void, and in the wafer cutting procedure, the spots are severed such that at least a portion of the spots overhangs the interconnect die edge.

3. The method of claim 1, wherein the wafer cutting procedure includes cutting through the void and the conformal electrically insulative coating.

4. The method of claim 1, wherein the spots are formed over and directly contact the conformal coating between the die pad and the interconnect die edge.

5. The method of claim 1, further comprising thinning the wafer from a backside thereof while the channel remains at least partially empty.

6. The method of claim 1, wherein the conformal coating is applied to a bottom surface of the channel.

7. A method for preparing a die for stacking and electrical connection, comprising:

performing a first wafer cutting procedure along a first saw street;

forming a channel defining an interconnect die edge and an empty space therein;

forming spots of a curable electrically conductive polymer material over die pads and extending over an interconnect die edge and at least partially over the empty space;

curing the conductive polymer material; and

in a second wafer cutting procedure thereafter severing the spots, wherein the second wafer cutting procedure defines a final extent of the spots relative to the interconnect die edge in an assembly of the die.

8. The method of claim 7, further comprising performing a single conformal dielectric coating procedure.

9. The method of claim 7, further comprising thinning the wafer subsequent to carrying out the first wafer cutting procedure.

10. The method of claim 7 wherein the first wafer cutting procedure is made to a depth greater than the eventual die thickness and less than the full wafer thickness, forming interconnect sidewalls.

11. A method of claim 7, wherein each of the spots bridge the channel prior to being severed, and after being severed the spots include overhang portions extending beyond an exposed portion of the interconnect die edge.

12. A method of claim 7, wherein the severed spots include overhang portions extending beyond an exposed surface of the conformal coating.

13. The method of claim 7, further comprising thinning the wafer from a backside thereof while the channel remains at least partially empty.

14. A method for preparing a die for stacking and electrical connection, comprising:

forming a channel at a front face of the wafer, the channel having a bottom surface disposed below the front face of the wafer, the channel at least partially defining an interconnect die edge of a die of the wafer and an empty space within the channel;

applying a conformal electrically insulative coating over at least the front face of the wafer and along the bottom surface of the channel and the interconnect die edge such that a portion of the channel remains empty;

applying electrically conductive spots over a die pad exposed at the front face of the wafer and at least partially over the conformal coating and empty space; and

thinning the wafer from a back face thereof up to at least the conformal coating at the bottom surface of the channel while the portion of the channel remains empty.

15. The method of claim 14, further comprising cutting through the spots, empty space and the conformal electrically insulative coating.

16. The method of claim 14, wherein the cutting step includes cutting through the spots such that at least a portion of the spots overhangs the interconnect die edge.

17. The method of claim 14, further comprising applying a die attach film to the wafer after the thinning step.

18. The method of claim 17, further comprising cutting through the spots and die attach film.

19. The method of claim 14, wherein the spots are formed such that they extend across the channel at least to an opposite interconnect die edge.