Semiconductor package having an antenna and manufacturing method thereof

• US 9,153,542 B2
• Filed: 08/01/2012
• Issued: 10/06/2015
• Est. Priority Date: 08/01/2012
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lin, I-Chia, Jou, Sheng-Jian, Yen, Han-Chee
• Primary Examiner(s): Tran, Long K
• Application Number:
  US13/564,702
• Publication Number:
  US 20140035097A1
• Time in Patent Office: 1,161 Days
• Field of Search: 257/531
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 21/0087 : Apparatus or processes specially adapted for manufacturing antenna arrays manufacturing waveguides H01P11/00
• CPC Class Codes: H01Q 21/064 : using horn or slot aerials slotted waveguides arrays H01Q21/005
• CPC Class Codes: H01Q 21/065 : Patch antenna array

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.

Claims

1. A semiconductor package comprising:

a first substrate including a ground layer;

an interposer disposed on an upper surface of the first substrate and having at least one opening;

a first die disposed in the at least one opening and coupled to the first substrate;

a second substrate coupled to the interposer, disposed over the first substrate and having an area less than an area of the first substrate;

a second die disposed on a lower surface of the second substrate;

a third die embedded within the second substrate;

an inductor disposed on an upper surface of the second substrate wherein the inductor is electrically connected to the second die and the third die;

a package body encapsulating portions of the first substrate, the interposer, the second substrate, the first die and the second die, the package body having a lateral surface and an upper surface; and

a metal layer disposed on the lateral surface and the upper surface of the package body wherein the metal layer is electrically connected to the first substrate and wherein the metal layer has voids that overlie the inductor.

2. The semiconductor package of claim 1, wherein the embedded third die has an active surface facing towards the first substrate.

3. The semiconductor package of claim 1, wherein the embedded third die has an active surface including bond pads which are exposed from the second substrate.

4. The semiconductor package of claim 3, further comprising a conductive path connecting the exposed bond pads with the inductor.

5. The semiconductor package of claim 1, further comprising an electrical frame, the electrical frame electrically connected to the ground layer and the metal layer.

6. The semiconductor package of claim 1, wherein the inductor is separated from the metal layer by the package body.

7. The semiconductor package of claim 1, wherein the voids determine a radiation distribution pattern.

8. The semiconductor package of claim 1, further comprising:

a dielectric layer covering the upper surface of the metal layer; and

a patterned metal layer formed on the dielectric layer.

9. A semiconductor package comprising:

a first substrate including a ground layer;

an interposer disposed on an upper surface of the first substrate;

a first die disposed in a space defined by the interposer and coupled to the first substrate;

a second substrate disposed over the first substrate and coupled to the interposer;

a second die disposed on a lower surface of the second substrate;

an inductor disposed on an upper surface of the second substrate and coupled to the second die;

a package body encapsulating portions of the first substrate, the interposer, the second substrate, the first die and the second die, the package body having a lateral surface and an upper surface; and

a metal layer disposed on the lateral surface and the upper surface of the package body wherein the metal layer is electrically connected to the first substrate and wherein the metal layer has voids that overlie the inductor.

10. The semiconductor package of claim 9, wherein the second substrate has an area less than an area of the first substrate.

11. The semiconductor package of claim 9, further comprising a third die embedded within the second substrate and electrically connected to the inductor and the second die.

12. The semiconductor package of claim 11, wherein the embedded third die has an active surface facing towards the first substrate.

13. The semiconductor package of claim 11, wherein the embedded third die has an active surface including bond pads which are exposed from the second substrate.

14. The semiconductor package of claim 13, further comprising a conductive path connecting the exposed bond pads with the inductor.

15. The semiconductor package of claim 9, further comprising an electrical frame, the electrical frame electrically connected to the ground layer and the metal layer.

16. The semiconductor package of claim 9, wherein the inductor is separated from the metal layer by the package body.

17. The semiconductor package of claim 9, wherein the voids determine a radiation distribution pattern.