Integrated circuit package including in-situ formed cavity

• US 9,153,551 B2
• Filed: 11/07/2014
• Issued: 10/06/2015
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Liang, Steve X.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US14/536,068
• Publication Number:
  US 20150061125A1
• Time in Patent Office: 333 Days
• Field of Search: 257/737
• US Class Current: 1/1
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 2224/81139 : Guiding structures on the body
• CPC Class Codes: H01L 2224/8114 : Guiding structures outside the body
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81207 : Thermosonic bonding
• CPC Class Codes: H01L 2224/814 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/81439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81464 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/8183 : Solid-solid interdiffusion
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/315 : the encapsulation having a cavity
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H03H 9/0523 : for flip-chip mounting
• CPC Class Codes: H03H 9/059 : consisting of mounting pads or bumps

Abstract

A flip chip packaged component includes a die having a first surface and a dielectric barrier disposed on the first surface of the die. The dielectric barrier at least partially surrounds a designated location on the first surface of the die. A plurality of bumps is disposed on the first surface of the die on an opposite side of the dielectric barrier from the designated location. The flip chip packaged component further includes a substrate having a plurality of bonding pads on a second surface thereof. A cavity is defined by the first surface of the die, the dielectric barrier, and the substrate. A molding compound encapsulates the die and at least a portion of the substrate.

Claims

1. A flip chip packaged component comprising:

a die having a first surface;

a dielectric barrier disposed on the first surface of the die, the dielectric barrier at least partially surrounding a designated location on the first surface of the die;

a plurality of bumps disposed on the first surface of the die, the plurality of bumps being located on an opposite side of the dielectric barrier from the designated location;

a substrate including a plurality of bonding pads on a second surface of the substrate, the die bonded to the substrate in a flip chip configuration, the plurality of bumps bonded to the plurality of bonding pads, the dielectric barrier contacting the substrate;

a cavity defined by the first surface of the die, the dielectric barrier, and the substrate, the cavity being proximate the designated location on the first surface of the die; and

a molding compound encapsulating the die and at least a portion of the substrate, the molding compound underfilling a portion of the die and contacting the opposite side of the dielectric barrier from the designated location, the dielectric barrier preventing the molding compound from entering the cavity.

2. The component of claim 1 wherein the plurality of bumps include a conductive material.

3. The component of claim 2 wherein the plurality of bumps include gold bumps.

4. The component of claim 3 wherein the plurality of bonding pads are gold-plated bonding pads.

5. The component of claim 2 wherein the plurality of bumps include copper pillar bumps.

6. The component of claim 1 wherein the cavity is free of the molding compound.

7. The component of claim 1 wherein the dielectric barrier includes SU8 polymer.

8. A flip chip semiconductor component package comprising:

a die having a plurality of connection bumps formed on a first surface thereof;

a substrate having a corresponding plurality of conductive bonding pads formed on a second surface thereof, the plurality of connection bumps on the first surface of the die bonded to the plurality of conductive bonding pads on the second surface of the substrate;

a dielectric barrier disposed on the first surface of the die, the dielectric barrier at least partially surrounding a designated location on the first surface of the die, the designated location being free of any of the plurality of connection bumps, the dielectric barrier bonded to the substrate with a gap-free bond;

a cavity defined by the dielectric barrier between the first surface of the die and the substrate; and

a molding compound encapsulating the die and at least a portion of the substrate, the molding compound underfilling a portion of the die, the dielectric barrier preventing the molding compound from entering the cavity.

9. The package of claim 8 wherein the plurality of conductive bonding pads are gold-plated bonding pads and the plurality of connection bumps include gold bumps.

10. The package of claim 8 wherein the die includes a MEMS device.

11. The package of claim 10 wherein the MEMS device is at least partially disposed within the designated location.

12. The package of claim 8 wherein the dielectric barrier completely surrounds the designated location.

13. The package of claim 8 wherein the dielectric barrier includes SU8 polymer.

14. A flip chip semiconductor component package comprising:

a die having a plurality of connection bumps formed on a first surface thereof;

a substrate having a corresponding plurality of conductive bonding pads formed on a second surface thereof, the plurality of connection bumps on the first surface of the die bonded to the plurality of conductive bonding pads on the second surface of the substrate;

a dielectric barrier disposed on the second surface of the substrate and bonded to the die with a gap-free bond;

a cavity defined by the dielectric barrier between the first surface of the die and the substrate; and

a molding compound encapsulating the die and at least a portion of the substrate, the molding compound underfilling a portion of the die, the dielectric barrier preventing the molding compound from entering the cavity.

15. The package of claim 14 wherein the dielectric barrier includes SU8 polymer.

16. The package of claim 14 wherein the plurality of conductive bonding pads are gold-plated bonding pads and the plurality of connection bumps include gold bumps.

17. The package of claim 14 wherein the die includes a MEMS device.

18. The package of claim 14 wherein the dielectric barrier completely surrounds the cavity.

19. The package of claim 18 wherein the cavity is free of any of the plurality of connection bumps.

20. The package of claim 14 wherein the cavity is a resonant cavity.