Electromigration immune through-substrate vias

• US 9,153,558 B2
• Filed: 08/02/2012
• Issued: 10/06/2015
• Est. Priority Date: 02/09/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Filippi, Ronald G., Fitzsimmons, John A., Kolvenbach, Kevin, Wang, Ping-Chuan
• Primary Examiner(s): Sun, Yu-Hsi D
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US13/565,416
• Publication Number:
  US 20120292763A1
• Time in Patent Office: 1,160 Days
• Field of Search: 257/621, 257/751, 257/E23.011, 257/E21.499, 438106-123, 438629-639, 438/653
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]

Abstract

A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Claims

1. A method of forming a semiconductor structure comprising:

forming at least one trench in a first substrate;

filling said at least one trench with a conductive liner material and a conductive via segment material, wherein said conductive liner material constitutes a conductive liner located on sidewalls of said at least one trench and said conductive via segment material completely or partially fills each cavity in said at least one trench; and

performing at least once a set of processing steps including;

recessing a portion of a material that fills each upper portion of said at least one trench;

depositing another conductive liner material on exposed sidewalls of each of said at least one trench; and

depositing another conductive via segment material in each of said at least one trench,

whereby at least one through-substrate via (TSV) structure is formed in said first substrate.

2. The method of claim 1, wherein said at least one trench extends from a first surface located on one side of said first substrate into said first substrate, wherein said method further comprises removing a portion of said first substrate from a surface located on an opposite side of said first substrate from said first surface, whereby said at least one TSV structure is exposed on a second surface of said first substrate after removal of said portion of said first substrate, and wherein said second surface is located on an opposite side of said first surface.

3. The method of claim 2, wherein said at least one TSV structure is an array of TSV structures, and said method further comprises forming an array of conductive bonding material structures on said second surface of said first substrate, wherein each of said array of conductive bonding material structures contacts a bottom surface of a TSV structure within said array of TSV structures.

4. The method of claim 3, further comprising bonding a second substrate or a packaging substrate to said first substrate through said array of conductive bonding material, wherein said array of TSV structures and said array of conductive bonding material structures provide a plurality of electrical connections between at least one semiconductor device in said first substrate and conductive structures located within said second substrate or within said packaging substrate.

5. The method of claim 1, wherein said TSV structure extends from a first surface located on one side of said first substrate to a second surface located on an opposite side of said first substrate, each of said at least one TSV structure comprising a plurality of conductive via segments that are vertically spaced from one another by at least one conductive liner portion.

6. The method of claim 5, wherein each vertically adjacent pair of said plurality of conductive via segments is spaced from each other by a conductive liner portion among said at least one conductive liner portion, wherein a bottom surface of one of said vertically adjacent pair of conductive via segments is in contact with an upper surface of said conductive liner portion and a top surface of the other of said vertically adjacent pair of conductive via segments is in contact with a lower surface of said conductive liner portion.

7. The method of claim 5, wherein said recessing of said portion of said material is set such that each conductive via segment within one of said at least one TSV structure has a vertical length that is less than a Blech length thereof for a maximum current density that said one of said at least one TSV structure is configured to flow within said first substrate.

8. The method of claim 7, further comprising:

determining a cross-sectional area per through-substrate via from a design of a semiconductor chip that is manufactured in said first substrate for each of said at least one TSV structure;

determining a maximum current from said design for each of said at least one TSV structure;

determining said Blech length for each of said at least one TSV structure, wherein said Blech length is determined by L_Blech=A_TSV×

(jL)_th/I_TSV, wherein L_Blech is said Blech length, A_TSV is said cross-sectional area, (jL)_th is a critical current density-length product for a material constituting said plurality of conductive via segments, and I_TSV is said maximum current.

9. The method of claim 8, wherein each of said at least one trench has a substantially same depth d0, and said method further comprises setting a total number of repetitions for performing of said set of processing steps at a positive integer N, wherein said (N+1) is a smallest integer that is equal to or greater than d0/min(L_Blech), wherein min(L_Blech) is a minimum of all Blech lengths of said at least one TSV.