Stacked packaging improvements

• US 9,153,562 B2
• Filed: 12/18/2014
• Issued: 10/06/2015
• Est. Priority Date: 11/03/2004
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Mitchell, Craig S., Beroz, Masud
• Primary Examiner(s): Le, Thao P
• Application Number:
  US14/574,988
• Publication Number:
  US 20150102508A1
• Time in Patent Office: 292 Days
• Field of Search: 257/678
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

In-process units include upper and lower dielectric substrates and a plurality of microelectronic elements disposed between the upper and lower substrates. Each of the upper and lower substrates includes a plurality of regions. Each region of the upper substrate is aligned with a corresponding region of the lower substrate. At least one of the microelectronic elements is disposed between the upper and lower substrates and each of the regions of the upper and lower substrates has interlayer connection terminals at the surface thereof. Vertically elongated electrical conductors are formed from copper and each extend in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and have an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.

Claims

1. An in-process unit including upper and lower dielectric substrates and a plurality of microelectronic elements disposed between a surface of the upper dielectric substrate and a surface of the lower dielectric substrate facing the surface of the upper dielectric substrate, each of the microelectronic elements comprising a semiconductor chip, and each of the upper and lower dielectric substrates including a plurality of regions, each region of the upper dielectric substrate being aligned with a corresponding region of the lower dielectric substrate with at least one of the microelectronic elements disposed therebetween, and each region of the upper dielectric substrate and each region of the lower dielectric substrate having interlayer connection terminals at the surface thereof,

the in-process unit further including vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and having an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.

2. The in-process unit of claim 1, wherein the end of each vertically elongated electrical conductor is a first end, each vertically elongated electrical conductor having a second end opposite the first end, the second end joined with an electrically conductive bonding material to one of the interlayer connection terminals of the dielectric substrate opposite from the first end.

3. The in-process unit of claim 2, wherein the electrically conductive bonding material forms a fillet encircling the end of each vertically elongated electrical conductors, the fillet facing and electrically coupled to the interlayer connection terminal of the dielectric substrate opposite from the dielectric substrate from which the electrically conductive bonding material projects.

4. The in-process unit of claim 1, wherein the vertically elongated electrical conductors are pins.

5. The in-process unit of claim 1, wherein the electrically conductive bonding material comprises solder.

6. The in-process unit of claim 1, further comprising an encapsulant disposed at least between the first and second dielectric substrates.

7. The in-process unit of claim 6, wherein the encapsulant overlies the microelectronic elements and at least substantially fills a volume between the upper and lower dielectric substrates.

8. The in-process unit of claim 2, wherein the second ends of the vertically elongated electrical conductors are joined by an electrically conductive bonding material with the interlayer connection terminals of the dielectric substrate away from which they extend.

9. The in-process unit of claim 2, wherein the vertically elongated electrical conductors are rodlike.

10. An in-process unit, comprising:

a lower dielectric substrate having a plurality of regions;

a plurality of upper dielectric substrates, each aligned with a respective region of the lower dielectric substrate; and

interlayer connection terminals disposed at each of the plurality of regions of the lower dielectric substrate and each of the plurality of upper dielectric substrates;

a plurality of microelectronic elements each comprising a semiconductor chip, each microelectronic element disposed between a surface of one of the upper dielectric substrates and a surface of the respective region of the lower dielectric substrate; and

vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of one of a region of the plurality of regions of the lower dielectric substrate and a dielectric substrate of the plurality of upper dielectric substrates, and each having an end joined with an electrically conductive bonding material to the interlayer connection terminal of an other one of the region of the plurality of regions of the lower dielectric substrate and the dielectric substrate of the plurality of upper dielectric substrates.

11. An in-process unit as claimed in claim 10, further comprising an encapsulant disposed at least between each of the upper dielectric substrates and the respective region of the lower dielectric substrate.

12. The in-process unit of claim 10, wherein the encapsulant overlies the microelectronic elements and at least substantially fills a volume between each of the upper dielectric substrates and the respective region of the lower dielectric substrate.

13. The in-process unit of claim 10, wherein the electrically conductive bonding material comprises solder, and wherein the vertically elongated electrical conductors are joined by the solder with an interlayer connection terminal of an opposite dielectric substrate from which the vertically elongated electrical conductors extend.

14. An in-process unit, comprising:

an upper dielectric substrate having a plurality of regions;

a plurality of lower dielectric substrates, each aligned with a respective region of the upper dielectric substrate;

interlayer connection terminals disposed at each region of the upper dielectric substrate and each of the plurality of lower dielectric substrates; and

a plurality of microelectronic elements, each disposed between a surface of one of the plurality of lower dielectric substrates and a surface of the respective region of the upper dielectric substrate, each of the microelectronic elements comprising a semiconductor chip; and

vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of one of a region of the plurality of regions of the upper dielectric substrate and a dielectric substrate of the plurality of lower dielectric substrates, and each having an end joined with an electrically conductive bonding material to the interlayer connection terminal of an other one of the region of the plurality of regions of the upper dielectric substrate and the dielectric substrate of the plurality of lower dielectric substrates.

15. An in-process unit as claimed in claim 14, further comprising an encapsulant disposed at least between each of the plurality of lower dielectric substrates and the respective region of the upper dielectric substrate.

16. The in-process unit of claim 14, wherein the encapsulant overlies the microelectronic elements and at least substantially fills a volume between the upper and lower dielectric elements.

17. The in-process unit of claim 14, wherein the electrically conductive bonding material comprises solder, and wherein the vertically elongated electrical conductors are joined by the solder with an interlayer connection terminal of an opposite dielectric substrate from which the vertically elongated electrical conductors extend.