Stacked packaging improvements
First Claim
1. An in-process unit including upper and lower dielectric substrates and a plurality of microelectronic elements disposed between a surface of the upper dielectric substrate and a surface of the lower dielectric substrate facing the surface of the upper dielectric substrate, each of the microelectronic elements comprising a semiconductor chip, and each of the upper and lower dielectric substrates including a plurality of regions, each region of the upper dielectric substrate being aligned with a corresponding region of the lower dielectric substrate with at least one of the microelectronic elements disposed therebetween, and each region of the upper dielectric substrate and each region of the lower dielectric substrate having interlayer connection terminals at the surface thereof,the in-process unit further including vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and having an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.
4 Assignments
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Accused Products
Abstract
In-process units include upper and lower dielectric substrates and a plurality of microelectronic elements disposed between the upper and lower substrates. Each of the upper and lower substrates includes a plurality of regions. Each region of the upper substrate is aligned with a corresponding region of the lower substrate. At least one of the microelectronic elements is disposed between the upper and lower substrates and each of the regions of the upper and lower substrates has interlayer connection terminals at the surface thereof. Vertically elongated electrical conductors are formed from copper and each extend in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and have an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.
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Citations
17 Claims
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1. An in-process unit including upper and lower dielectric substrates and a plurality of microelectronic elements disposed between a surface of the upper dielectric substrate and a surface of the lower dielectric substrate facing the surface of the upper dielectric substrate, each of the microelectronic elements comprising a semiconductor chip, and each of the upper and lower dielectric substrates including a plurality of regions, each region of the upper dielectric substrate being aligned with a corresponding region of the lower dielectric substrate with at least one of the microelectronic elements disposed therebetween, and each region of the upper dielectric substrate and each region of the lower dielectric substrate having interlayer connection terminals at the surface thereof,
the in-process unit further including vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and having an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.
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10. An in-process unit, comprising:
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a lower dielectric substrate having a plurality of regions; a plurality of upper dielectric substrates, each aligned with a respective region of the lower dielectric substrate; and interlayer connection terminals disposed at each of the plurality of regions of the lower dielectric substrate and each of the plurality of upper dielectric substrates; a plurality of microelectronic elements each comprising a semiconductor chip, each microelectronic element disposed between a surface of one of the upper dielectric substrates and a surface of the respective region of the lower dielectric substrate; and vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of one of a region of the plurality of regions of the lower dielectric substrate and a dielectric substrate of the plurality of upper dielectric substrates, and each having an end joined with an electrically conductive bonding material to the interlayer connection terminal of an other one of the region of the plurality of regions of the lower dielectric substrate and the dielectric substrate of the plurality of upper dielectric substrates. - View Dependent Claims (11, 12, 13)
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14. An in-process unit, comprising:
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an upper dielectric substrate having a plurality of regions; a plurality of lower dielectric substrates, each aligned with a respective region of the upper dielectric substrate; interlayer connection terminals disposed at each region of the upper dielectric substrate and each of the plurality of lower dielectric substrates; and a plurality of microelectronic elements, each disposed between a surface of one of the plurality of lower dielectric substrates and a surface of the respective region of the upper dielectric substrate, each of the microelectronic elements comprising a semiconductor chip; and vertically elongated electrical conductors formed from copper, each extending in a vertical direction away from the surface of one of a region of the plurality of regions of the upper dielectric substrate and a dielectric substrate of the plurality of lower dielectric substrates, and each having an end joined with an electrically conductive bonding material to the interlayer connection terminal of an other one of the region of the plurality of regions of the upper dielectric substrate and the dielectric substrate of the plurality of lower dielectric substrates. - View Dependent Claims (15, 16, 17)
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Specification