Thin film transistor and method for manufacturing the same

• US 9,153,651 B2
• Filed: 02/01/2013
• Issued: 10/06/2015
• Est. Priority Date: 09/24/2012
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Lim, Sang Chul, Oh, Ji-Young, Ahn, Seongdeok, Cho, Kyoung Ik, Lee, Sang Seok, Koo, Jae Bon
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US13/757,699
• Publication Number:
  US 20140084283A1
• Time in Patent Office: 977 Days
• Field of Search: 438/158, 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided are a thin film transistor and a method for manufacturing the same. The thin film transistor manufacturing method includes forming a gate electrode on a substrate, forming an active layer that is adjacent to the gate electrode and includes an oxide semiconductor, forming an oxygen providing layer on the active layer, forming a gate dielectric between the gate electrode and the active layer, forming source and drain electrodes coupled to the active layer, forming a planarizing layer covering the gate electrode and the gate dielectric, forming a hole exposing the active layer, and performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen.

Claims

1. A method for manufacturing a thin film transistor, comprising:

forming a gate electrode on a substrate;

forming an active layer that is adjacent to the gate electrode and comprises an oxide semiconductor;

forming an oxygen providing layer on the active layer;

forming a gate dielectric between the gate electrode and the active layer;

forming source and drain electrodes coupled to the active layer;

forming a planarizing layer covering the gate electrode and the gate dielectric;

forming a hole in the planarizing layer exposing the active layer; and

performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen, thereby providing oxygen atoms of the atmosphere of oxygen to the active layer though the hole.

2. The method of claim 1, wherein the oxygen providing layer comprises a metal oxide that emits oxygen at a first temperature.

3. The method of claim 2, wherein the oxygen providing layer comprises AgO.

4. The method of claim 2, wherein the heat treatment process is performed at a second temperature higher than the first temperature.

5. The method of claim 1, wherein oxygen atoms in the oxygen providing layer are supplied into the active layer by the heat treatment process.

6. The method of claim 1, wherein the hole in the planarizing layer passes through the gate dielectric and the oxygen providing layer to expose a part of an upper surface of the active layer.

7. The method of claim 1, further comprising forming a buffer layer on the substrate.

8. The method of claim 1, wherein the forming of the gate dielectric comprises:

forming a first insulating layer between the gate electrode and the active layer;

forming a second insulating layer on the first insulating layer; and

forming a third insulating layer between the first insulating layer and the second insulating layer,

wherein the first and second insulating layers comprise inorganic materials and the third insulating layer comprises organic materials.

9. The method of claim 1, wherein the hole in the planarizing layer passes through the oxygen providing layer.

10. A method for manufacturing a thin film transistor, comprising:

forming a gate electrode on a substrate;

forming an active layer that is adjacent to the gate electrode and comprises an oxide semiconductor;

forming an oxygen providing layer on the active layer;

forming a gate dielectric between the gate electrode and the active layer;

forming source and drain electrodes coupled to the active layer;

forming a planarizing layer covering the gate electrode and the gate dielectric;

forming a hole exposing the active layer; and

performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen,

wherein oxygen atoms from the atmosphere of oxygen are supplied into the active layer through the hole.

11. The method of claim 10, wherein the hole passes through the planarizing layer and the oxygen providing layer.

12. The method of claim 11, wherein the hole further passes through the gate dielectric.

13. A method for manufacturing a thin film transistor, comprising:

forming a gate electrode on a substrate;

forming an active layer that is adjacent to the gate electrode and comprises an oxide semiconductor;

forming an oxygen providing layer on the active layer;

forming a gate dielectric between the gate electrode and the active layer;

forming source and drain electrodes coupled to the active layer;

forming a planarizing layer covering the gate electrode and the gate dielectric;

forming a hole exposing the active layer; and

performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen, thereby providing oxygen from the atmosphere of oxygen to the active layer through the hole,

wherein the hole passes through the planarizing layer, the gate dielectric, and the oxygen providing layer to expose a part of an upper surface of the active layer.