Tuning tensile strain on FinFET

• US 9,153,668 B2
• Filed: 05/23/2013
• Issued: 10/06/2015
• Est. Priority Date: 05/23/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Chen, Guan-Lin, Hsu, Ting-Hung, Huang, Jiun-Jia, Lin, Zhi-Chang
• Primary Examiner(s): PARENDO, KEVIN A
• Application Number:
  US13/901,399
• Publication Number:
  US 20140346607A1
• Time in Patent Office: 866 Days
• Field of Search: 438/308
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

Claims

1. A method of forming an integrated circuit, comprising:

forming a fin having a gate region;

forming a dummy gate over the gate region;

forming source/drain regions on opposing sides of the gate region;

forming spacers over the fin, the spacers adjacent to the dummy gate;

depositing a dielectric over the source/drain regions and adjacent the spacers;

removing the dummy gate, thereby exposing a sidewall of each of the spacers facing the gate region; and

while the sidewall of the spacers is exposed, performing an annealing process, the annealing process contracting the dielectric and deforming the spacers, the deforming the spacers enlarging a distance between the spacers.

2. The method of claim 1, further comprising performing the annealing process at a temperature of between 500°

C. to about 650°

C.

3. The method of claim 1, further comprising performing the annealing process for a time of between 60 minutes to 120 minutes.

4. The method of claim 1, further comprising performing the annealing process at a pressure of 1 atmosphere.

5. The method of claim 1, further comprising performing the annealing process to shrink the dielectric between 15% to 18% relative to a size of the dielectric prior to the annealing process.

6. The method of claim 1, further comprising performing the annealing process to reduce a height and a width of the dielectric.

7. The method of claim 1, wherein the annealing process outgases at least one of nitrogen and hydrogen from the dielectric.

8. The method of claim 1, further comprising, after performing the annealing process, constructing a gate electrode structure over the gate region between the spacers.

9. The method of claim 1, further comprising contracting the dielectric to draw opposing ones of the spacers away from each other.

10. The method of claim 1, further comprising deforming the spacer inwardly toward the dielectric, a middle portion of the spacer deformed more than top and bottom portions of the spacer.

11. A method of forming an integrated circuit, the method comprising:

providing a substrate having a fin, the fin having a source region, a drain region, and a gate region interposed between the source region and the drain region;

forming a dielectric layer over the source region and the drain region, the gate region being free of the dielectric layer, thereby defining an opening over the gate region;

contracting the dielectric layer, thereby expanding the opening, the contracting being performed while sidewalls of the opening are exposed; and

forming a conductive material over the gate region of the fin within the opening.

12. The method of claim 11, wherein the forming the dielectric layer comprises:

forming a dummy gate over the gate region;

forming spacers along opposing sides of the dummy gate;

forming a dielectric material on opposing sides of the dummy gate; and

removing the dummy gate.

13. The method of claim 11, wherein the contracting is performed at least in part by annealing.

14. The method of claim 13, wherein the annealing outgases at least one of nitrogen and hydrogen from the dielectric layer.

15. A method of forming an integrated circuit, the method comprising:

forming spacers and a dielectric layer over a fin, an area between adjacent spacers defining an opening, the dielectric layer being absent in the opening, sidewalls of the opening being exposed;

after the forming, contracting the dielectric layer, thereby expanding the opening and deforming the spacers; and

after the contracting, forming a gate electrode within the opening.

16. The method of claim 15, wherein the contracting is performed at least in part by outgassing the dielectric layer.

17. The method of claim 16, wherein the outgassing comprises outgassing at least one of nitrogen and hydrogen.

18. The method of claim 15, wherein the contracting reduces a size of the dielectric layer between 15% and 18%.

19. The method of claim 15, wherein the contracting decreases a height of the dielectric layer.

20. The method of claim 15, wherein the contracting comprises annealing, the annealing outgassing nitrogen or hydrogen from the dielectric layer.