Non-intrusive monitoring and control of integrated circuits

• US 9,154,137 B2
• Filed: 05/19/2014
• Issued: 10/06/2015
• Est. Priority Date: 07/04/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Olgiati, Andrea, Baker, Matthew Pond, Teig, Steven
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US14/281,262
• Publication Number:
  US 20150008957A1
• Time in Patent Office: 505 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/3003 Monitoring arrangements specially adapted to the computing system or computing system component being monitored
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Claims

1. An application-specific integrated circuit (ASIC) comprising:

a plurality of non-configurable circuits customized for performing operations for a particular use;

a set of reconfigurable circuits for configurably performing operations of a user design based on configuration data; and

a configuration and monitoring network for receiving incremental sets of configuration data while the set of reconfigurable circuits is performing operations of the user design, each incremental set of data for configuring the configuration and monitoring network (i) to monitor a set of signals received at the set of reconfigurable circuits from one or more non-configurable circuits in the plurality of the non-configurable circuits of the ASIC and (ii) to take a set of actions when values of the monitored signals satisfy a set of conditions.

2. The ASIC of claim 1, wherein the incremental sets of configuration data further comprise one ore more incremental set of configuration data for configuring the configuration and monitoring network (i) to monitor a set of signals received at the set of reconfigurable circuits from one or more reconfigurable circuits in the set of the reconfigurable circuits of the ASIC and (ii) to take a set of actions when values of the monitored signals satisfy a set of conditions.

3. The ASIC of claim 1, wherein the configuration and monitoring network comprises a trace buffer to store data, wherein the set of actions comprises (i) sampling values of one or more signals in the set of signals and (ii) storing the sampled values in the trace buffer.

4. The ASIC of claim 1, wherein the configuration and monitoring network comprises a set of output lines, wherein the set of actions comprises (i) sampling values of one or more signals in the set of signals and (ii) sending the values to a particular output line of the configuration and monitoring network.

5. The ASIC of claim 1, wherein the configuration and monitoring network comprises a set of output lines, wherein the set of actions comprises sending a predetermined signal to a particular output line of the configuration and monitoring network.

6. The ASIC of claim 1, wherein the effect of the predetermined signal is to halt the operations of the ASIC.

7. The ASIC of claim 1 further comprising a controller for sending the incremental sets of configuration data to the configuration and monitoring network.

8. The ASIC of claim 1, wherein the controller is further for receiving signals for the configuration and monitoring network.

9. The ASIC of claim 1, wherein the configuration and monitoring network comprises a plurality of reconfigurable circuits, wherein configuring the configuration and monitoring network comprises utilizing incremental sets of configuration data to reconfigure said reconfigurable circuits of the configuration and monitoring network for monitoring for different sets of signals and taking actions when values of the monitored signals satisfy a set of conditions.

10. A method of monitoring operations of an integrated circuit (IC), the IC comprising a set of configurable circuits for configurably performing a set of operations based on configuration data, the method comprising:

loading a first set of configuration data into the IC for configuring a plurality of configurable circuits in the set of configurable circuits for performing operations of a user design;

receiving a definition of (i) a first event based on values of a first set of signals in the user design and (ii) a first set of actions to take when the first event occurs;

generating an incremental second set of configuration data based on the definition of the first event and the first set of actions;

while the IC is performing the operations of the user design, loading the incremental second set of configuration data into the IC to monitor for the first event and to take the first set of actions when the first event occurs;

receiving a definition of (i) a second event based on values of a second set of signals in the user design and (ii) a second set of actions to take when the second event occurs;

generating an incremental third set of configuration data based on the definition of the second event and the second set of actions; and

while the IC is performing the operations of the user design, loading the incremental third set of configuration data into the IC to monitor for the second event and to take the second set of actions when the second event occurs.

11. The method of claim 10, wherein the IC further comprises a configuration and monitoring network for (i) receiving configuration data sets, (ii) monitoring for events, and (iii) taking actions after a monitored event occurs.

12. The method of claim 11, wherein configuration and monitoring network comprises a set of reconfigurable circuits, wherein the second and third incremental configuration data sets comprise configuration data for reconfiguring the reconfigurable circuits of the configuration and monitoring network.

13. The method of claim 11, wherein loading the incremental second and third sets of configuration data into the IC does not replace the first set of configuration data.

14. The method of claim 11, wherein the first set of configuration data is generated from the user design;

wherein generating the incremental second and third sets of configuration data does not require modifying the user design.

15. The method of claim 11, wherein the first set of configuration data is generated by compiling the user design specified in register-transfer language (RTL), wherein generating the incremental second and third sets of configuration data does not require recompiling the user design.

16. A non-transitory machine readable medium for monitoring operations of an integrated circuit (IC), the IC comprising a set of configurable circuits for configurably performing a set of operations based on configuration data, the program executable by at least one processor, the program comprising sets of instructions for:

loading a first set of configuration data into the IC for configuring a plurality of configurable circuits in the set of configurable circuits for performing operations of a user design;

receiving a definition of (i) a first event based on values of a first set of signals in the user design and (ii) a first set of actions to take when the first event occurs;

generating an incremental second set of configuration data based on the definition of the first event and the first set of actions;

loading, while the IC is performing the operations of the user design, the incremental second set of configuration data into the IC to monitor for the first event and to take the first set of actions when the first event occurs;

receiving a definition of (i) a second event based on values of a second set of signals in the user design and (ii) a second set of actions to take when the second event occurs;

generating an incremental third set of configuration data based on the definition of the second event and the second set of actions; and

loading, while the IC is performing the operations of the user design, the incremental third set of configuration data into the IC to monitor for the second event and to take the second set of actions when the second event occurs.

17. The non-transitory machine readable medium of claim 16, wherein the IC further comprises a configuration and monitoring network for (i) receiving configuration data sets, (ii) monitoring for events, and (iii) taking actions after a monitored event occurs.

18. The non-transitory machine readable medium of claim 17, wherein configuration and monitoring network comprises a set of reconfigurable circuits, wherein the second and third incremental configuration data sets comprise configuration data for reconfiguring the reconfigurable circuits of the configuration and monitoring network.

19. The non-transitory machine readable medium of claim 16, wherein loading the incremental second and third sets of configuration data into the IC does not replace the first set of configuration data.

20. The non-transitory machine readable medium of claim 16, wherein the first set of configuration data is generated from the user design;

wherein generating the incremental second and third sets of configuration data does not require modifying the user design.

21. The non-transitory machine readable medium of claim 16, wherein the first set of configuration data is generated by compiling the user design specified in register-transfer language (RTL), wherein generating the incremental second and third sets of configuration data does not require recompiling the user design.