Packaging to reduce stress on microelectromechanical systems

• US 9,156,673 B2
• Filed: 09/18/2011
• Issued: 10/13/2015
• Est. Priority Date: 09/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryzek, Janusz, Bloomsburgh, John Gardner, Acar, Cenk
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US13/821,586
• Publication Number:
  US 20130341737A1
• Time in Patent Office: 1,486 Days
• Field of Search: 257/669, 257/674, 257/690, 257/735, 438/461, 438/611
• US Class Current: 1/1
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 3/0072 For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
• CPC Class Codes: B81B 7/0016 Protection against shocks or vibrations, e.g. vibration damping
• CPC Class Codes: B81B 7/0051 between the package lid and the substrate
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2203/0785 Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit.

Claims

1. An apparatus, comprising:

a via wafer including a main portion and an elongate arm having a first portion extending away from the main portion of the via wafer and a second portion extending about the main portion of the via wafer and separate from the main portion of the via wafer by a gap; and

a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the via wafer;

an application specific integrated circuit (ASIC) having a first surface coupled to the elongate arm of the via wafer using a first electrical interconnect and a second surface opposite to the first surface, the second surface having a second electrical interconnect centrally located on the second surface to couple the ASIC to a substrate,

wherein the elongate arm and the location of the second electrical interconnect are configured to protect the microelectromechanical layer from deformation or stress.

2. The apparatus of claim 1, wherein the elongate arm is part of a plurality of elongate arms, wherein for each respective elongate arm on a side of the via wafer, there is an opposing elongate arm on an opposite side of the via wafer.

3. The apparatus of claim 1, wherein the ASIC is coupled to the substrate using a cluster of electrical interconnects centrally disposed on the second surface of the ASIC.

4. The apparatus of claim 1, wherein the first surface of the ASIC is coupled to a distal end of the second portion of the elongate arm of the via wafer.

5. The apparatus of claim 1, wherein the microelectromechanical layer is coupled to the main portion of the via wafer using a central anchor.

6. The apparatus of claim 5, wherein the central anchor is configured to dispose the microelectromechanical layer away from the via wafer by a distance.

7. The apparatus of claim 1, including a cap coupled to the via wafer and configured to enclose the microelectromechanical layer between the cap and the via wafer.

8. The apparatus of claim 7, wherein the cap is coupled to the main portion of the via wafer.

9. The apparatus of claim 8, wherein the elongate arm is located outside of the cap.