Adaptive voltage scaling based on the results of forward error correction processing

• US 9,158,356 B2
• Filed: 06/28/2011
• Issued: 10/13/2015
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: Infinera Corp.
• Original Assignee: Infinera Corp.
• Inventors: Wu, Yuejian, Thomson, Sandy, Sun, Han Henry
• Primary Examiner(s): Britt, Cynthia
• Assistant Examiner(s): NGUYEN, THIEN DANG
• Application Number:
  US13/170,747
• Publication Number:
  US 20130007516A1
• Time in Patent Office: 1,568 Days
• Field of Search: 714/708
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

Claims

1. A device comprising:

a voltage regulator circuit to output a supply voltage;

a data processing circuit, coupled to the voltage regulator circuit, to receive data, process the data to obtain processed data, and output the processed data, where power for the data processing circuit is received from the supply voltage;

an error correction circuit, coupled to receive the processed data from the data processing circuit, to correct errors in the processed data based on the processed data to obtain error-corrected data, and to output, from the device, an error-corrected version of the processed data;

an error monitor circuit, coupled to the error correction circuit, to output an first signal indicative of a level of the errors in the processed data;

a timing sensor circuit that outputs a second signal indicative of a timing margin available in the data processing circuit, the timing margin being indicative of a difference between a time for the data processing circuit to perform a function in a clock period and the clock period; and

a control circuit to receive the first and second signals to control the voltage regulator circuit to adjust, based on the first and second signals, the supply voltage output by the voltage regulator circuit.

2. The device of claim 1, where the error correction circuit corrects the errors in the processed data in accordance with a forward error correction technique.

3. The device of claim 1, where the error signal, output from the error monitor circuit, indicates a quantity of bit errors over a time period or a quantity of bit errors relative to a quantity of bits in the processed data.

4. The device of claim 1, where the control circuit controls the voltage regulator circuit to lower the supply voltage when the level of errors is below a threshold.

5. The device of claim 1, where the control circuit controls the voltage regulator circuit to raise the supply voltage when the level of errors is above a threshold.

6. The device of claim 1, where the device includes a single integrated circuit chip.

7. A method, performed by a device, comprising:

detecting errors, using a forward error correction technique, in data received from a data processing circuit;

quantifying a level of the detected errors;

measuring timing margins in the data processing circuit, the timing margins being indicative of differences between respective times for the data processing circuit to perform a corresponding one of a plurality of functions in a clock period and the clock period;

adjusting a voltage, used to power the data processing circuit, based on the quantified level of the detected errors and the measured timing margins;

correcting the detected errors based on the received data to obtain error-corrected data; and

outputting the error corrected data from the device.

8. The method of claim 7, further comprising:

quantifying the level of the detected errors as a quantity of bit errors per unit time period or as a quantity of bit errors relative to a quantity of bits in the data.

9. The method of claim 7, where adjusting the voltage used to power the data processing circuit based on the quantified level of the detected errors and the measured timing margins further includes:

controlling a voltage regulator circuit to decrease a voltage level supplied to the data processing circuit when the quantified level of the detected errors is below a threshold.

10. The method of claim 9, where adjusting the voltage used to power the data processing circuit based on the quantified level of the detected errors and the measured timing margins further includes:

controlling the voltage regulator to increase the voltage level supplied to the data processing circuit when the quantified level of the detected errors is not below the threshold.

11. The method of claim 7, further comprising:

detecting errors for a plurality of data streams, where the plurality of data streams include the received data;

correcting the detected errors, for the plurality of data streams, to obtain a plurality of error-corrected data streams; and

outputting the error-corrected plurality of data streams from the device.

12. An integrated circuit comprising:

a data processing circuit to receive a plurality of input data signals, process the plurality of input data signals, and output the processed plurality of input data signals as a plurality of processed data signals;

an error correction circuit to receive the plurality of processed data signals, the error correction circuit including;

a forward error correction component to correct errors, in accordance with a forward error correction technique, in the plurality of processed data signals based on the plurality of processed data signals and to output a plurality of error-corrected data signals, and

a bit error rate monitor to output a first signal indicative of a level of errors corrected by the forward error correction component;

a timing sensor circuit that outputs a second signal indicative of a timing margin available in the data processing circuit, the timing margin being indicative of a difference between a time for the data processing circuit to perform a function in a clock period and the clock period;

a voltage regulator circuit to output a supply voltage to the data processing circuit;

a control circuit to control a level of the supply voltage, output from the voltage regulator circuit, based on the first and second signals; and

a plurality of output ports to output the plurality of error-corrected data signals from the integrated circuit.

13. The integrated circuit of claim 12, where the error rate signal indicates a quantity of bit errors over a time period or a quantity of bit errors relative to a quantity of bits in the plurality of processed data signals.

14. The integrated circuit of claim 12, where the control circuit controls the voltage regulator circuit to lower the supply voltage when the level of errors is below a threshold.

15. The integrated circuit of claim 12, where the control circuit controls the voltage regulator to raise the supply voltage when the level of errors is not below a threshold.

16. The integrated circuit of claim 12, where the control circuit additionally controls the voltage regulator circuit to adjust the supply voltage based on an operating temperature of the integrated circuit.

17. The integrated circuit of claim 12, where the integrated circuit has a System-on-Chip (SoC) design.