System and method for conveying service latency requirements for devices connected to low power input/output sub-systems

• US 9,158,357 B2
• Filed: 12/28/2012
• Issued: 10/13/2015
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jeyaseelan, Jaya L., Weyhing, Linda, Nalawadi, Rajeev, Cooper, Barnes, Varma, Suraj, Idan, Nevo, Poisner, David
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US13/730,625
• Publication Number:
  US 20140189391A1
• Time in Patent Office: 1,019 Days
• Field of Search: 713/300, 713/320
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.

Claims

1. A method for managing power, comprising:

communicating a latency tolerance value, wherein the latency tolerance value is;

associated with a first value stored in a software latency register for a device connected to a platform if a software latency tolerance register mode is active; and

associated with a second value stored in a hardware latency register if a host controller is active.

2. The method of claim 1, wherein the latency tolerance value is sent to a power management controller.

3. The method of claim 1, further comprising:

communicating the first value stored in the software latency register if the software latency tolerance register mode is not active and the host controller is not active.

4. The method of claim 1, further comprising:

mapping a resource space in the software latency register for the device using a BIOS/platform driver.

5. The method of claim 4, wherein the mapping is achieved using an advanced configuration and power interface device description for the device.

6. The method of claim 1, further comprising:

updating the first value stored in the software latency register when the device is in an active state.

7. The method of claim 1, wherein a universal asynchronous receiver/transmitter driver for the device is used to update the first value stored in the software latency register.

8. The method of claim 1, further comprising:

updating the first value stored in the software latency register with a no requirement value when the device is idle.

9. An apparatus, comprising:

logic at least partially implemented in hardware, the logic configured to;

communicate a latency tolerance value, wherein the latency tolerance value is;

associated with a first value stored in a software latency register for a device connected to a platform if a software latency tolerance register mode is active; and

associated with a second value stored in a hardware latency register if a host controller is active.

10. The apparatus of claim 9, wherein the latency tolerance value is sent to a power management controller.

11. The apparatus of claim 9, wherein the logic is further configured to:

communicate the first value stored in the software latency register if the software latency tolerance register mode is not active and the host controller is not active.

12. The apparatus of claim 9, wherein the logic is further configured to:

map a resource space in the software latency register for the device using a BIOS/platform driver.

13. The apparatus of claim 12, wherein the mapping is achieved using an advanced configuration and power interface device description for the device.

14. The apparatus of claim 9, wherein the logic is further configured to:

update the first value stored in the software latency register when the device is in an active state.

15. The apparatus of claim 14, wherein a universal asynchronous receiver/transmitter driver for the device is used to update the first value stored in the software latency register.

16. The apparatus of claim 9, wherein the logic is further configured to:

update the first value stored in the software latency register with a no requirement value when the device is idle.

17. A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause an apparatus to:

communicate a latency tolerance value, wherein the latency tolerance value is;

associated with a first value stored in a software latency register for a device connected to a platform if a software latency tolerance register mode is active; and

associated with a second value stored in a hardware latency register if a host controller is active.

18. The computer readable medium of claim 17, wherein the latency tolerance value is sent to a power management controller.

19. The computer readable medium of claim 17, further comprising instructions that, when executed by a processor, cause the apparatus to:

communicate the first value stored in the software latency register if the software latency tolerance register mode is not active and the host controller is not active.

20. The computer readable medium of claim 17, further comprising instructions that, when executed by a processor, cause the apparatus to:

map a resource space in the software latency register for the device using a BIOS/platform driver.

21. The computer readable medium of claim 20, wherein the mapping is achieved using an advanced configuration and power interface device description for the device.

22. The computer readable medium of claim 17, further comprising instructions that, when executed by a processor, cause the apparatus to:

update the first value stored in the software latency register when the device is in an active state.

23. The computer readable medium of claim 22, wherein a universal asynchronous receiver/transmitter driver for the device is used to update the first value stored in the software latency register.

24. The computer readable medium of claim 17, further comprising instructions that, when executed by a processor, cause the apparatus to:

update the first value stored in the software latency register with a no requirement value when the device is idle.

25. An apparatus, comprising:

a circuit for communicating a latency tolerance value, wherein the latency tolerance value is;

associated with a first value stored in a software latency register for a device connected to a platform if a software latency tolerance register mode is active; and

associated with a second value stored in a hardware latency register if a host controller is active.

26. The apparatus of claim 25, further comprising:

a circuit for communicating the first value stored in the software latency register if the software latency tolerance register mode is not active and the host controller is not active.

27. The apparatus of claim 25, further comprising:

a circuit for mapping a resource space in the software latency register for the device using a BIOS/platform driver.