Flash subsystem organized into pairs of upper and lower page locations

• US 9,158,623 B2
• Filed: 11/11/2014
• Issued: 10/13/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Nemazie, Siamack, Mandapuram, Anilkumar
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US14/538,659
• Publication Number:
  US 20150067449A1
• Time in Patent Office: 336 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes

Abstract

A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Claims

1. A memory system comprising:

a flash subsystem configured to save pages of information, the pages of information organized into blocks, each page of information including one or more codewords, each codeword having data and error correction code (ECC), each of the pages of information having an upper page of data and a lower page of data, the flash subsystem configured to save upper pages in upper page locations and to save lower pages in lower page locations, the flash subsystem including more than one flash die, a first block being in a first flash die and a second block being in a second flash die, wherein the lower page of data is saved in the first block and the upper page of data is saved in the second block, and

a flash controller coupled to the flash subsystem and operable to save pages of information in the flash subsystem, the flash controller operable to save a page of information having a codeword with data and ECC,

wherein the codeword is split between an upper page location and a lower page location of the flash subsystem and a lower page of data of the first block being paired with an upper page of data of the second block causes substantially concurrent reading of the lower and upper pages of data.

2. The memory system, as recited in claim 1, wherein the flash controller is configured to write pages in sequential order.

3. The memory system, as recited in claim 1, further including a buffer coupled to the flash controller and made of flash-backed memory.

4. The memory system, as recited in claim 1, further including a buffer coupled to the flash controller wherein the buffer includes magnetic random access memory (MRAM).

5. The memory system, as recited in claim 4, wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).

6. The memory system, as recited in claim 1, wherein the first flash die and the second flash die are coupled to different flash channels.

7. The memory system, as recited in claim 1, wherein the the ECC uses Bose, Chaudhuri, and Hocquenghem (BCH) code.

8. The memory system, as recited in claim 7, wherein the ECC is a low-density parity-check (LDPC) code.

9. A memory system comprising:

a flash subsystem organized into upper page locations and lower page locations, the upper and lower page locations defining a page location configured to save a page, pages being organized into blocks, the upper page locations configured to save first segments and the lower page locations configured to save second segments, the first and second segments including split data and error correction code (ECC) and forming at least a part of a page, the flash subsystem including more than one flash die, a first block being in a first flash die and a second block being in a second flash die; and

a flash controller coupled to the flash subsystem and operable to save a page in the flash subsystem, the page having a first segment and a second segment with split data and ECC, the flash controller being operable to save the first segment into an upper page location of the flash subsystem and to save the second segment into a lower page location of the flash subsystem,

wherein the first segment is saved in the first block in the first flash die and the second segment is saved in the second block in the second flash die, the first segment being paired with the second segment causing substantially concurrent reading of the first and second segments.

10. The memory system, as recited in claim 9, wherein the flash controller is configured to write pages in sequential order.

11. The memory system, as recited in claim 9, further including a buffer coupled to the flash controller and made of flash-backed memory.

12. The memory system, as recited in claim 9, further including a buffer coupled to the flash controller wherein the buffer includes magnetic random access memory (MRAM).

13. The memory system, as recited in claim 12, wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).

14. The memory system, as recited in claim 9, wherein the first flash die and the second flash die are coupled to different flash channels.

15. The memory system, as recited in claim 9, wherein the ECC uses Bose, Chaudhuri, and Hocquenghem (BCH) code.

16. The memory system, as recited in claim 15, wherein the ECC is a low-density parity-check (LDPC) code.