Nonvolatile memory system with migration manager

• US 9,158,671 B2
• Filed: 08/16/2012
• Issued: 10/13/2015
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ryu, Jun Kil, Kwon, MoonSang
• Primary Examiner(s): BRADLEY, MATTHEW A
• Application Number:
  US13/586,967
• Publication Number:
  US 20130046920A1
• Time in Patent Office: 1,153 Days
• Field of Search: 711/118
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Disclosed is a memory system that includes a nonvolatile memory having a main region and a cache region; and a memory controller having migration manager managing a migration operation that moves data from cache region to the main region by referencing a Most Recently Used/Least Recently Used (MRU/LRU) list.

Claims

1. A memory system comprising:

a nonvolatile memory including a main region and a cache region; and

a memory controller configured to control operation of the nonvolatile memory and including a migration manager that manages file data migration from the cache region to the main region with reference to a Most Recently Used (MRU)/Least Recently Used (LRU) list containing entries for file data units stored in the cache region, wherein the migration manager defines the MRU/LRU list as an arrangement of highest to lowest queue locations, such that entries related to more recently written file data units are arranged higher in queue location than entries related to more recently read file data units, and entries related to more recently read file data units are arranged higher in queue location than entries related to less recently written file data units and entries related to less recently read file data units.

2. The memory system of claim 1, wherein an entry for a most recently written file data unit is placed by the migration manager in the highest queue location of the MRU/LRU list.

3. The memory system of claim 1, wherein for each successive write operation, an entry for a corresponding file data unit written to the cache region is placed in the highest queue location of the MRU/LRU list by the migration manager, and existing entries to the MRU/LRU list are shifted down towards the lowest queue location by the migration manager.

4. The memory system of claim 3, wherein for each read operation directed to a file data unit stored in the cache region, an entry for a corresponding file data read unit is shifted up towards the highest queue location of the MRU/LRU list by the migration manager but no higher in the MRU/LRU list than entries for the more recently written file data units.

5. The memory system of claim 4, wherein the main region comprises multi-level memory cells (MLC), and the cache region comprises single-level memory cells (SLC).

6. The memory system of claim 1, wherein the nonvolatile memory stores input data received from an external device during a write operation in the cache region, and subsequently moves the input data from the cache region to the main region by operation of the migration manager with reference to the MRU/LRU list.

7. The memory system of claim 6, wherein the migration manager starts execution of the migration operation when an amount of used space in the cache region exceeds a first threshold, and the migration manager stops the migration operation when the amount of used space in the cache region falls below a second threshold.

8. The memory system of claim 6, wherein the migration manager starts execution of the migration operation when an amount of available space in the cache region falls below a first threshold, and the migration manager stops the migration operation when the amount of available space in the cache region exceeds a second threshold.

9. The memory system of claim 1, wherein the nonvolatile memory is a flash memory.

10. The memory system of claim 1, wherein the cache region and the main region are implemented on a single memory chip.

11. The memory system of claim 1, wherein the cache region and the main region are respectively implemented on separate memory chips.

21. The memory system of claim 1, wherein the nonvolatile memory includes a plurality of cell strings connected to a bit line, each cell string including a plurality of memory cells connected to one another in series, each memory cell being connected to each of a plurality of word lines, respectively.

12. A memory system comprising:

a flash memory having a main region configured from multi-level memory cells (MLC) and a cache region configured from single-level memory cells (SLC); and

a memory controller configured to control operation of the flash memory and including a migration manager that manages file data migration from the cache region to the main region with reference to a Most Recently Used (MRU)/Least Recently Used (LRU) list containing entries for file data units stored in the cache region, wherein the memory controller temporarily uses some of the MLC as part of the cache region if an insufficient number of the SLC are available when a file data unit is stored in the cache region.

13. The memory system of claim 12, wherein the migration manager defines the MRU/LRU list as an arrangement of highest to lowest queue locations, such that entries related to more recently written file data units are arranged higher in queue location than entries related to more less recently read file data units, and entries related to more recently read file data units are arranged higher in queue location than entries related to less recently written file data units and entries related to less recently read file data units.

14. The memory system of claim 13, wherein an entry for a most recently written file data unit is placed by the migration manager in the highest queue location of the MRU/LRU list.

15. The memory system of claim 14, wherein for each successive write operation, an entry for a corresponding file data unit written to the cache region is placed in the highest queue location of the MRU/LRU list by the migration manager, and existing entries to the MRU/LRU list are shifted down towards the lowest queue location by the migration manager.

16. The memory system of claim 15, wherein for each read operation directed to a file data unit stored in the cache region, an entry for a corresponding file data read unit is shifted up towards the highest queue location of the MRU/LRU list by the migration manager but no higher in the MRU/LRU list than entries for the more recently written file data units.

17. The memory system of claim 12, wherein the memory controller stores input data received from an external device in the SLC region during a write operation and subsequently moves the stored input data from the SLC region to the MLC region in accordance with the MRU/LRU list.

18. The memory system of claim 12, wherein the migration manager starts execution of the migration operation when an amount of used space in the cache region exceeds a first threshold, and stops the migration operation when the amount of used space in the cache region falls below a second threshold.

19. The memory system of claim 12, wherein the SLC and MLC are commonly implemented on a single memory chip.

20. The memory system of claim 12, wherein the SLC and MLC are respectively implemented on different memory chips.

22. The memory system of claim 12, wherein the flash memory includes a plurality of cell strings connected to a bit line, each cell string including a plurality of memory cells connected to one another in series, each memory cell being connected to each of a plurality of word lines, respectively.