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Dynamically controlling cache size to maximize energy efficiency

  • US 9,158,693 B2
  • Filed: 10/31/2011
  • Issued: 10/13/2015
  • Est. Priority Date: 10/31/2011
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a plurality of cores each to independently execute instructions;

    a cache memory coupled to the plurality of cores and including a plurality of partitions; and

    a power controller coupled to the plurality of cores and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage lower than an operating voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the plurality of cores are power gated.

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