Dynamically controlling cache size to maximize energy efficiency
First Claim
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1. A processor comprising:
- a plurality of cores each to independently execute instructions;
a cache memory coupled to the plurality of cores and including a plurality of partitions; and
a power controller coupled to the plurality of cores and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage lower than an operating voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the plurality of cores are power gated.
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Abstract
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
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11 Claims
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1. A processor comprising:
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a plurality of cores each to independently execute instructions; a cache memory coupled to the plurality of cores and including a plurality of partitions; and a power controller coupled to the plurality of cores and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage lower than an operating voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the plurality of cores are power gated. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A processor comprising:
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a plurality of cores each to independently execute instructions; a cache memory coupled to the plurality of cores and including a plurality of partitions; and a power controller coupled to the plurality of cores and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered to maintain a state of at least one core of the plurality of cores when the processor is in a package low power state in which the plurality of cores are power gated, wherein the plurality of partitions corresponds to ways of the cache memory, and the power controller is to dynamically enable or disable each of the plurality of ways independently, cause at least one first way of the cache memory to be enabled with a retention voltage when the processor is in the package low power state, and cause at least one second way of the cache memory to be disabled while the at least one first way is enabled with the retention voltage when the processor is in the package low power state, wherein the at least one second way is to be flushed to a system memory prior to being disabled; at least one graphics engine; and a ring interconnect to couple the plurality of cores, the cache memory and the at least one graphics engine. - View Dependent Claims (9, 10, 11)
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Specification