Deterministic message processing in a direct memory access adapter
First Claim
1. An apparatus for deterministic message processing in a direct memory access (DMA) adapter, the DMA adapter utilizing a first-in-first-out (FIFO) message queue for processing packets received by the DMA adapter, the DMA adapter using a head pointer, a tail pointer, a sub-head pointer, and a sub-tail pointer to point to particular packets within the FIFO message queue, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
- incrementing from the sub-head pointer, the sub-tail pointer until encountering an out-of-sequence packet;
consuming packets between the sub-head pointer and the sub-tail pointer including incrementing with the consumption of each packet, the sub-head pointer until determining that the sub-head pointer is equal to the sub-tail pointer;
in response to determining that the sub-head pointer is equal to the sub-tail pointer, determining whether the head pointer is pointing to the next in-sequence packet;
if the head pointer is pointing to the next in-sequence packet, resetting the sub-head pointer and the sub-tail pointer to the head pointer; and
if the head pointer is not pointing to the next in-sequence packet, resetting the sub-head pointer and the sub-tail pointer to the next in-sequence packet.
1 Assignment
0 Petitions
Accused Products
Abstract
Deterministic message processing in a direct memory access (DMA) adapter includes the DMA adapter incrementing from a sub-head pointer, a sub-tail pointer until encountering an out-of-sequence packet. The DMA adapter also consumes packets between the sub-head pointer and the sub-tail pointer including incrementing with the consumption of each packet, the sub-head pointer until determining that the sub-head pointer is equal to the sub-tail pointer. In response to determining that the sub-head pointer is equal to the sub-tail pointer, the DMA adapter determines whether the head pointer is pointing to the next in-sequence packet. If the head pointer is pointing to the next in-sequence packet, the DMA adapter resets the sub-head pointer and the sub-tail pointer to the head pointer. If the head pointer is not pointing to the next in-sequence packet, the DMA adapter resets the sub-head pointer and the sub-tail pointer to the next in-sequence packet.
11 Citations
12 Claims
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1. An apparatus for deterministic message processing in a direct memory access (DMA) adapter, the DMA adapter utilizing a first-in-first-out (FIFO) message queue for processing packets received by the DMA adapter, the DMA adapter using a head pointer, a tail pointer, a sub-head pointer, and a sub-tail pointer to point to particular packets within the FIFO message queue, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
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incrementing from the sub-head pointer, the sub-tail pointer until encountering an out-of-sequence packet; consuming packets between the sub-head pointer and the sub-tail pointer including incrementing with the consumption of each packet, the sub-head pointer until determining that the sub-head pointer is equal to the sub-tail pointer; in response to determining that the sub-head pointer is equal to the sub-tail pointer, determining whether the head pointer is pointing to the next in-sequence packet; if the head pointer is pointing to the next in-sequence packet, resetting the sub-head pointer and the sub-tail pointer to the head pointer; and if the head pointer is not pointing to the next in-sequence packet, resetting the sub-head pointer and the sub-tail pointer to the next in-sequence packet. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computer program product deterministic message processing in a direct memory access (DMA) adapter, the DMA adapter utilizing a first-in-first-out (FIFO) message queue for processing packets received by the DMA adapter, the DMA adapter using a head pointer, a tail pointer, a sub-head pointer, and a sub-tail pointer to point to particular packets within the FIFO message queue, the computer program product disposed upon a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:
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incrementing from the sub-head pointer, the sub-tail pointer until encountering an out-of-sequence packet; consuming packets between the sub-head pointer and the sub-tail pointer including incrementing with the consumption of each packet, the sub-head pointer until determining that the sub-head pointer is equal to the sub-tail pointer; in response to determining that the sub-head pointer is equal to the sub-tail pointer, determining whether the head pointer is pointing to the next in-sequence packet; if the head pointer is pointing to the next in-sequence packet, resetting the sub-head pointer and the sub-tail pointer to the head pointer; and if the head pointer is not pointing to the next in-sequence packet, resetting the sub-head pointer and the sub-tail pointer to the next in-sequence packet. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification