Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices
First Claim
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1. An apparatus comprising:
- a plurality of memory cells including a plurality of data cells, a first supplemental cell and a second supplemental cell; and
a refresh logic coupled to the plurality of memory cells, the refresh logic configured to;
calibrate a first refresh rate, a second refresh rate slower than the first refresh rate, and a third refresh rate slower than the second refresh rate, by;
sampling a data cell of the plurality of data cells, the first supplemental cell, and the second supplemental cell,calibrating the second refresh rate based on a comparison between a sampled data from the data cell to a sampled data from the first supplemental cell, andcalibrating the third refresh rate based on a comparison between the sampled data from the data cell to a sampled data from the second supplemental cell, andrefresh the plurality of data cells at the first refresh rate,refresh the first supplemental cell at the second refresh rate,refresh the second supplemental cell at the third refresh rate,increase the first refresh rate responsive to reading a first value from the first supplemental cell, the first value indicative of loss of charge in the first supplemental cell below a predetermined level, anddecrease the first refresh rate responsive to reading a second value from the second supplemental cell, the second value indicative of retaining of charge in the second supplemental cell not below the predetermined level.
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Abstract
A mechanism for facilitating improved refresh schemes for memory devices is described. In one embodiment, an apparatus includes a memory device having refresh logic and memory cells, the memory cells including data cells and supplemental cells, the supplemental cells to be observed. The supplemental cells emulate a decay characteristic of the data cells performing regular refresh operations according to an existing refresh policy. The apparatus may further include the refresh logic to receive, from the supplemental cells, observation data relating to decaying of the supplemental cells, and correlate the observation data to data cell performance. The refresh logic to generate a policy recommendation based on the observation data collected by the supplemental cells.
16 Citations
23 Claims
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1. An apparatus comprising:
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a plurality of memory cells including a plurality of data cells, a first supplemental cell and a second supplemental cell; and a refresh logic coupled to the plurality of memory cells, the refresh logic configured to; calibrate a first refresh rate, a second refresh rate slower than the first refresh rate, and a third refresh rate slower than the second refresh rate, by; sampling a data cell of the plurality of data cells, the first supplemental cell, and the second supplemental cell, calibrating the second refresh rate based on a comparison between a sampled data from the data cell to a sampled data from the first supplemental cell, and calibrating the third refresh rate based on a comparison between the sampled data from the data cell to a sampled data from the second supplemental cell, and refresh the plurality of data cells at the first refresh rate, refresh the first supplemental cell at the second refresh rate, refresh the second supplemental cell at the third refresh rate, increase the first refresh rate responsive to reading a first value from the first supplemental cell, the first value indicative of loss of charge in the first supplemental cell below a predetermined level, and decrease the first refresh rate responsive to reading a second value from the second supplemental cell, the second value indicative of retaining of charge in the second supplemental cell not below the predetermined level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system comprising:
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a processor; and a memory device comprising; a plurality of memory cells including a plurality of data cells, a first supplemental cell a second supplemental cell; and a refresh logic coupled to the plurality of memory cells, the refresh logic configured to; calibrate a first refresh rate, a second refresh rate slower than the first refresh rate, and a third refresh rate slower than the second refresh rate, by; sampling a data cell of the plurality of data cells, the first supplemental cell, and the second supplemental cell, calibrating the second refresh rate based on a comparison between a sampled data from the data cell to a sampled data from the first supplemental cell, and calibrating the third refresh rate based on a comparison between the sampled data from the data cell to a sampled data from the second supplemental cell, refresh the plurality of data cells at a first refresh rate, refresh the first supplemental cell at a second refresh rate slower than the first refresh rate, refresh the second supplemental cell at a third rate slower than the first refresh rate and the second refresh rate, increase the first refresh rate responsive to reading a first value from the first supplemental cell, the first value indicative of loss of charge in the first supplemental cell below a predetermined level, and decrease the first refresh rate responsive to reading a second value from the second supplemental cell, the second value indicative of retaining of charge in the second supplemental cell not below the predetermined level. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A method comprising:
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calibrating a first refresh rate, a second refresh rate slower than the first refresh rate, and a third refresh rate slower than the second refresh rate, by; sampling a data cell of the plurality of data cell, the first supplemental cell, and the second supplemental cell, calibrating the second refresh rate based on a comparison between a sampled data from the data cell to a sampled data from the first supplemental cell, and calibrating the third refresh rate based on a comparison between the sampled data from the data cell to a sampled data from the second supplemental cell; refreshing the plurality of data cells at a first refresh rate; refreshing a first supplemental cell at a second refresh rate slower than the first refresh rate; refreshing a second supplemental cell at a third rate slower than the first refresh rate and the second refresh rate; increasing the first refresh rate responsive to reading a first value from the first supplemental cell, the first value indicative of loss of charge in the first supplemental cell below a predetermined level; and decreasing the first refresh rate responsive to reading a second value from the second supplemental cell, the second value indicative of retaining of charge in the second supplemental cell not below the predetermine level. - View Dependent Claims (20, 21, 22, 23)
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Specification
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Current AssigneeLattice Semiconductor Corporation
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Original AssigneeLattice Semiconductor Corporation
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InventorsIsaac, Roger, Ruberg, Alan
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Primary Examiner(s)MACKALL, LARRY T
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Application NumberUS13/173,302Publication NumberTime in Patent Office1,566 DaysField of Search711/106US Class Current1/1CPC Class CodesG11C 11/40615 Internal triggering or timi...G11C 11/40618 Refresh operations over mul...G11C 2211/4061 Calibration or ate or cycle...
