Non-volatile memory interface

• US 9,159,419 B2
• Filed: 03/31/2014
• Issued: 10/13/2015
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Intelligent Intellectual Property Holdings LLC
• Inventors: Nellans, David, Wipfel, Robert
• Primary Examiner(s): Tseng, Cheng-Yuan
• Assistant Examiner(s): Perez-Velez, Rocio Del Mar
• Application Number:
  US14/231,437
• Publication Number:
  US 20140297929A1
• Time in Patent Office: 561 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for a memory controller. An apparatus includes a volatile memory medium located on a memory module. An apparatus includes a non-volatile memory medium located on a memory module. A memory controller is located on a memory module. A memory controller may be configured to provide access to at least a non-volatile memory medium over a direct wire interface with a processor.

Claims

1. An apparatus comprising:

a volatile memory medium located on a memory module;

a non-volatile memory medium located on the memory module;

a memory controller located on the memory module, the memory controller configured to provide access to at least the non-volatile memory medium over a direct wire interface with a processor by way of a command protocol, the direct wire interface comprising a control path for the command protocol; and

a logic engine comprised within the memory controller, wherein the logic engine is configured to perform one or more of;

generating data bit patterns according to the command protocol; and

interpreting data bit patterns according to the command protocol.

2. The apparatus of claim 1, wherein the memory controller is configured to store data in and read data from the volatile memory medium and the non-volatile memory medium to execute commands received from the processor over the direct wire interface.

3. The apparatus of claim 1, wherein the memory module comprises a dual in-line memory module with a series of integrated circuits comprising the volatile memory medium and the non-volatile memory medium.

4. The apparatus of claim 1, wherein the memory controller of the memory module comprises a receiving module configured to receive a command from a memory controller of the processor over the direct wire interface.

5. The apparatus of claim 4, wherein the memory controller of the memory module comprises an execution module configured to execute the command within the memory controller of the memory module in response to determining that the memory controller of the memory module is capable of satisfying the command.

6. The apparatus of claim 5, wherein the command comprises a synchronous command and the execution module is configured to execute the command asynchronously using the non-volatile memory medium in response to determining that the memory controller of the memory module is capable of satisfying the command asynchronously.

7. The apparatus of claim 1, wherein the memory controller comprises a notification module configured to notify a memory controller of the processor of one or more memory attributes of the non-volatile memory medium such that the memory controller of the processor directs data to one of the non-volatile memory medium, the volatile memory medium, a memory division of the non-volatile memory medium, and a memory division of the volatile memory medium based on the memory attributes.

8. The apparatus of claim 1, wherein the memory controller is configured to store an index for a logical to physical translation layer for the non-volatile memory medium in the volatile memory medium.

9. The apparatus of claim 1, wherein the memory controller further comprises:

a storage module configured to store data in the non-volatile memory medium in a format that associates the data with respective logical memory addresses of the non-volatile memory medium and with sequence indicators indicating an ordered sequence of operations for the non-volatile memory medium;

an index module configured to maintain an index, in the volatile memory medium, of associations between the logical memory addresses of the data and physical storage locations storing the data on the non-volatile memory medium; and

an index reconstruction module configured to reconstruct the index using the logical memory addresses and the sequence indicators associated with the data of the non-volatile memory medium, wherein the index reconstruction module replays a sequence of changes made to the index using the logical memory addresses and the sequence indicators associated with the data of the non-volatile memory medium.

10. The apparatus of claim 1, wherein the processor communicates with the volatile memory medium using a different protocol than the processor uses to communicate with the non-volatile memory medium.

11. The apparatus of claim 1, wherein the volatile memory medium comprises one or more of dynamic random access memory (DRAM), static random access memory (SRAM), and buffer random access memory (BRAM).

12. The apparatus of claim 1, wherein the wire interface comprises one of:

a (QuickPath Interconnect) QPI point-to-point processor interface; and

a HyperTransport point-to-point processor interface.

13. The apparatus of claim 1, wherein the logic engine is configured to perform one or more of:

re-transmitting commands over the direct wire interface; and

processing out-of order commands.

14. A system comprising:

one or more processors comprising a processor memory controller; and

a dual in-line memory module comprising;

one or more volatile memory integrated circuits;

one or more non-volatile memory integrated circuits;

a non-volatile memory controller in communication with the processor memory controller over a wire interface of the one or more processors by way of a command protocol, the wire interface comprising a control path for the command protocol; and

a logic engine comprised within the non-volatile memory controller, wherein the logic engine is configured to perform one or more of;

generating data bit patterns according to the command protocol; and

interpreting data bit patterns according to the command protocol.

15. The system of claim 14, wherein the non-volatile memory controller is configured to store data in and read data from the one or more volatile memory integrated circuits and the one or more non-volatile memory integrated circuits to execute commands received from the processor memory controller over the wire interface.

16. The system of claim 14, further comprising the wire interface of the processor, the wire interface comprising one or more of a QuickPath Interconnect (QPI) and a HyperTransport point-to-point interface.

17. A method comprising:

receiving commands from a memory controller of a processor to a memory module over a wire interface of the processor by way of a command protocol, the wire interface comprising a control path for the command protocol, and a logic engine comprised within the memory module generating data bit patterns according to the command protocol and interpreting data bit patterns according to a command protocol;

storing data in a non-volatile memory element of the memory module to satisfy at least one of the commands; and

storing data in a volatile memory element of the memory module to satisfy at least one of the commands.

18. The method of claim 17, wherein the data stored in the non-volatile memory element comprises data of one or more write commands received for the non-volatile memory element from the memory controller of the processor.

19. The method of claim 18, wherein the data stored in the volatile memory element comprises a mapping between logical memory addresses of the data stored in the non-volatile memory element and physical storage locations of the data in the non-volatile memory element.

20. The method of claim 17, wherein at least one of the commands comprises a synchronous command and the method further comprises executing the synchronous command asynchronously using the non-volatile memory element in response to determining that a non-volatile memory controller of the memory module is capable of satisfying the synchronous command asynchronously.

21. The method of claim 17, further comprising notifying the memory controller of the processor, from the memory module, of memory attributes of the non-volatile memory element, the memory controller directing data to one of the non-volatile memory element, the volatile memory element, a memory division of the non-volatile memory element, and a memory division of the volatile memory element based on the memory attributes.

22. The method of claim 17, further comprising operating one or more memory maintenance functions on the non-volatile memory element, wherein a non-volatile memory controller of the memory module operates the one or more memory maintenance functions one of independently of the memory controller of the processor and in response to receiving one or more memory management commands from the memory controller of the processor.

23. The method of claim 17, wherein the wire interface comprises one of:

a (QuickPath Interconnect) QPI point-to-point processor interface; and

a HyperTransport point-to-point processor interface.

24. The method of claim 17, wherein the logic engine is configured to perform one or more of:

re-transmitting commands over the direct wire interface; and

processing out-of order commands.