Methods and apparatus for in-pixel filtering in focal plane arrays including apparatus and method for counting pulses representing an analog signal

• US 9,159,446 B2
• Filed: 11/06/2013
• Issued: 10/13/2015
• Est. Priority Date: 07/01/2011
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Schultz, Kenneth I., Tyrrell, Brian, Kelly, Michael W., Colonero, Curtis, Candell, Lawrence M., Mooney, Daniel
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US14/073,338
• Publication Number:
  US 20140321600A1
• Time in Patent Office: 706 Days
• Field of Search: 250/214.R, 250/208.1, 250/214.1, 327/514, 327/515, 377/118, 377/129
• US Class Current: 1/1
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03K 23/548 Reversible counters
• CPC Class Codes: H03M 1/001 Analogue/digital/analogue conversion
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

Claims

1. An apparatus for counting pulses representing an analog signal, the apparatus comprising:

(A) a photodetector array comprising at least one photodetector to produce a photocurrent in response to detection of light; and

(B) an integrated circuit operably coupled to the photodetector array, the integrated circuit comprising a plurality of unit cells, wherein at least one unit cell in the plurality of unit cells comprises;

(i) a converter to convert the photocurrent from the at least one photodetector in the photodetector array to series of pulses;

(ii) a first counter to count first pulses in the series of pulses in response to a first clock selection signal; and

(iii) a second counter to count second pulses in the series of pulses in response to a second clock selection signal.

2. The apparatus of claim 1, wherein the at least one photodetector is configured to produce the photocurrent at an intermediate frequency in response to detection of a modulated signal and a local oscillator signal.

3. The apparatus of claim 1, wherein the first clock selection signal is configured to be selected independently of the second clock selection signal.

4. The apparatus of claim 1, wherein the first counter is configured to switch between a count mode and a read-out mode in response to a change in the first clock selection signal.

5. The apparatus of claim 1, wherein the at least one unit cell further comprises:

(iv) logic, operably coupled to the first counter, to select one of a plurality of counting modes of the first counter in response to a first control signal.

6. The apparatus of claim 5, wherein the plurality of counting modes comprises:

a count-up mode in which the first counter increments a count in response to the pulses in the series of pulses,

a count-down mode in which the first counter decrements a count in response to the pulses in the series of pulses,

a shift mode in which the first counter shifts data, and

a ripple-count mode in which the first counter provides the second pulses to the second counter.

7. The apparatus of claim 6, wherein, in the shift mode, the first counter is configured to shift data to at least one other unit cell in the plurality of unit cells.

8. The apparatus of claim 1, further comprising:

(D) a clock to provide an in-phase clock signal to clock the first counter and a quadrature clock signal to clock the second counter.

9. A method for counting pulses representing an analog signal, the apparatus comprising:

(A) producing a photocurrent, with at least one photodetector in a photodetector array, in response to detection of light; and

(B) converting the photocurrent to a series of pulses with a converter in a unit cell in a plurality of unit cells operably coupled to the photodetector array;

(C) counting first pulses in the series of pulses with a first counter in the unit cell in response to a first clock selection signal; and

(D) counting second pulses in the series of pulses with a second counter in the unit cell in response to a second clock selection signal.

10. The method of claim 9, wherein (A) comprises:

producing the photocurrent at an intermediate frequency in response to detection of a modulated signal and a local oscillator signal by the at least one photodetector.

11. The method of claim 9, further comprising:

selecting the first clock selection signal independently of the second clock selection signal.

12. The method of claim 9, further comprising:

switching the first counter between a count mode and a read-out mode in response to a change in the first clock selection signal.

13. The method of claim 9, further comprising:

selecting one of a plurality of counting modes of the first counter in response to a first control signal.

14. The method of claim 13, wherein the plurality of counting modes comprises:

a count-up mode in which the first counter increments a count in response to the pulses in the series of pulses,

a count-down mode in which the first counter decrements a count in response to the pulses in the series of pulses,

a shift mode in which the first counter shifts data, and

a ripple-count mode in which the first counter provides the second pulses to the second counter.

15. The method of claim 14, further comprising, in the shift-register mode:

shifting data from the first counter to at least one other unit cell in the plurality of unit cells.

16. The method of claim 9, further comprising:

generating an in-phase clock signal;

generating a quadrature clock signal, and wherein;

(C) comprises counting the first pulses at a first rate determined by the in-phase clock signal, and

(D) comprises counting the second pulses at a second rate determined by the quadrature clock signal.

17. An apparatus for counting pulses representing an amplitude of optical radiation, the apparatus comprising:

a plurality of photodetectors comprising at least one photodetector to produce an analog signal representing the amplitude of the optical radiation; and

an integrated circuit operably coupled to the plurality of photodetectors, the integrated circuit comprising a plurality of unit cells, wherein at least one unit cell in the plurality of unit cells comprises;

a converter to convert the analog signal from the at least one photodetector in the photodetector array to series of pulses;

a plurality of counters comprising at least one counter, operably coupled to the converter, to count pulses in the series of pulses and to read-out a count representing the pulses in the series of pulses in response to a read-out clock; and

a first multiplexer, operably coupled to the converter and to the at least one counter in the plurality of counters, to couple one of the series of pulses and the read-out clock to the plurality of counters in response to a clock selection signal.

18. The apparatus of claim 17, wherein the at least one unit cell further comprises:

a second multiplexer, operably coupled to the plurality of counters, to select an operating mode of the at least one counter in the plurality of counters.

19. The apparatus of claim 18, wherein the second multiplexer is configured to select the operating mode from among at least two of:

a count-up mode in which the first counter increments a count in response to the pulses in the series of pulses,

a count-down mode in which the first counter decrements a count in response to the pulses in the series of pulses,

a shift mode in which the first counter shifts data, and

a ripple-count mode in which the first counter provides the second pulses to the second counter.

20. The apparatus of claim 17, wherein the at least one unit cell further comprises:

transfer circuitry, operably coupled to the plurality of counters, to shift the count from the at least one counters to another plurality of counters in another unit cell in the plurality of unit cells.