Automatic word line leakage measurement circuitry

• US 9,159,452 B2
• Filed: 11/14/2008
• Issued: 10/13/2015
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yamada, Shigekazu
• Primary Examiner(s): Lau, Tung S
• Application Number:
  US12/271,140
• Publication Number:
  US 20100125429A1
• Time in Patent Office: 2,524 Days
• Field of Search: 702/64
• US Class Current: 1/1
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device.

Claims

1. A memory device, comprising:

a plurality of memory cells;

a plurality of word lines coupled to the plurality of memory cells; and

a leakage measurement circuit coupled to the plurality of word lines, the leakage measurement circuit operable to generate a reference current and to determine whether a leakage current on the one of the plurality of word lines is acceptable relative to the reference current, wherein the leakage measurement circuit comprises;

a current generation circuit to generate the reference current at one of a plurality of current values;

a leakage test circuit coupled to the current generation circuit and the plurality of word lines, the leakage test circuit operable to compare the leakage current on each of the plurality of word lines with the reference current;

a selection circuit coupled to the leakage test circuit and operable to generate a signal indicating whether the leakage current on at least one of the plurality of word lines is acceptable; and

a plurality of measurement enable circuits and a plurality of comparing circuits, and wherein;

each of the plurality of measurement enable circuits coupled to a respective one of the plurality of word lines and a respective one of the plurality of comparing circuits,

each of the plurality of measurement enable circuits operable to set a word line voltage on the respective one of the plurality of word lines to a respective voltage level by coupling the respective one of the plurality of word lines to the respective voltage level responsive to a first control signal,

each of the plurality of measurement enable circuits further operable to couple the respective one of the plurality of word lines to the respective one of the plurality of comparing circuits responsive to the first control signal,

each of the plurality of measurement enable circuits further operable to decouple the respective one of the plurality of word lines from the respective voltage level responsive to a second control signal, and

each of the plurality of measurement enable circuits further operable to supply the reference current to the respective one of the plurality of word lines by coupling the respective one of the plurality of word lines to the current generation circuit responsive to the second control signal.

2. The memory device of claim 1 wherein the leakage measurement circuit operable to generate the reference current at one of a plurality of current values and to determine whether the leakage current on one of the plurality of word lines is acceptable relative to the reference current at one of the plurality of current values.

3. The memory device of claim 1 wherein each of the plurality of comparing circuits operable to compare the word line voltage on a respective one of the plurality of word lines with a respective voltage level to indicate whether the leakage current on the respective one of the plurality of word lines is acceptable.

4. The memory device of claim 1 wherein the selection circuit comprises a multiplexer having a plurality of input terminals each of which coupled to an output terminal of a respective one of the plurality of comparing circuits, and an output terminal to generate the signal indicating whether a respective leakage current on at least one of the plurality of word lines is acceptable.

6. The memory device of claim 3 wherein:

each of the plurality of measurement enable circuits comprises;

a first switch having a control terminal to receive the first control signal, a first signal terminal coupled to a respective one of the plurality of word lines, and a second signal terminal coupled to a respective one of the plurality of comparing circuits,

a second switch having a control terminal to receive the second control signal, a first signal terminal coupled to the current generation circuit, and a second signal terminal coupled to the second signal terminal of the first switch, and

a third switch having a control terminal to receive the second control signal, a first signal terminal coupled to a respective voltage level, and a second signal terminal coupled to the second signal terminal of the first switch, and wherein;

each of the plurality of comparing circuits comprises a sense amplifier having a first input terminal coupled to the second signal terminal of the first switch, a second input terminal coupled to the respective voltage level, and an output terminal to generate the signal indicating whether a respective leakage current on the respective one of the plurality of word lines is acceptable.

7. The memory device of claim 6 wherein:

the first switch and the second switch comprise a n-type metal-oxide-semiconductor (NMOS) transistor,

the third switch comprises a p-type metal-oxide-semiconductor (PMOS) transistor, and

the sense amplifier comprises a comparator.

5. The memory device of 1 wherein the memory device comprises a flash memory device.

8. A computer system, comprising:

an input device;

an output device;

a processor coupled to the input device and the output device; and

a memory device coupled to the processor and having a plurality of word lines, the memory device operable to generate a reference current in the memory device and to determine whether a leakage current on the one of the plurality of word lines is acceptable relative to the reference current, wherein the memory device comprises;

a current generation circuit to generate the reference current at one of the plurality of current values;

a leakage test circuit coupled to the current generation circuit and the plurality of word lines, the leakage test circuit operable to compare the leakage current on each of the plurality of word lines with the reference current;

a selection circuit coupled to the leakage test circuit and operable to generate a signal indicating whether the leakage current on at least one of the plurality of word lines is acceptable; and

a plurality of measurement enable circuits and a plurality of comparing circuits, wherein;

each of the plurality of measurement enable circuits coupled to a respective one of the plurality of word lines and a respective one of the plurality of comparing circuits,

each of the plurality of measurement enable circuits operable to set a word line voltage on the respective one of the plurality of word lines to a respective voltage level by coupling the respective one of the plurality of word lines to the respective voltage level responsive to a first control signal,

each of the plurality of measurement enable circuits further operable to couple the respective one of the plurality of word lines to the respective one of the plurality of comparing circuits responsive to the first control signal,

each of the plurality of measurement enable circuits further operable to decouple the respective one of the plurality of word lines from the respective voltage level responsive to a second control signal, and

each of the plurality of measurement enable circuits further operable to supply the reference current to the respective one of the plurality of word lines by coupling the respective one of the plurality of word lines to the current generation circuit responsive to the second control signal.

9. The computer system of claim 8 wherein the memory device operable to generate the reference current at one of the plurality of current values, and wherein determining whether the leakage current on one of the plurality of word lines is acceptable relative to the reference current comprises determining whether the leakage current on one of the plurality of word lines is acceptable relative to the reference current at one of the plurality of current values.

10. The computer system of claim 8 wherein each of the plurality of comparing circuits operable to compare the word line voltage on a respective one of the plurality of word lines with a respective voltage level to indicate whether the leakage current on the respective one of the plurality of word lines is acceptable.

11. The computer system of claim 8 wherein the selection circuit comprises a multiplexer having a plurality of input terminals each of which coupled to an output terminal of a respective one of the plurality of comparing circuits, and an output terminal to generate the signal indicating whether a respective leakage current on at least one of the plurality of word lines is acceptable.

13. The computer system of claim 10 wherein:

each of the plurality of measurement enable circuits comprises;

a first switch having a control terminal to receive the first control signal, a first signal terminal coupled to a respective one of the plurality of word lines, and a second signal terminal coupled to a respective one of the plurality of comparing circuits,

a second switch having a control terminal to receive the second control signal, a first signal terminal coupled to the current generation circuit, and a second signal terminal coupled to the second signal terminal of the first switch, and

a third switch having a control terminal to receive the second control signal, a first signal terminal coupled to a respective voltage level, and a second signal terminal coupled to the second signal terminal of the first switch, and wherein;

each of the plurality of comparing circuits comprises a sense amplifier having a first input terminal coupled to the second signal terminal of the first switch, a second input terminal coupled to the respective voltage level, and an output terminal to generate the signal indicating whether a respective leakage current on the respective one of the plurality of word lines is acceptable.

14. The computer system of claim 13 wherein:

the first switch and the second switch comprise a n-type metal-oxide-semiconductor (NMOS) transistor,

the third switch comprises a p-type metal-oxide-semiconductor (PMOS) transistor, and

the sense amplifier comprises a comparator.

12. The computer system of 8 wherein the memory device comprises a flash memory device.