Method of forming a germanium-containing FinFET

• US 9,159,552 B2
• Filed: 12/27/2013
• Issued: 10/13/2015
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fan, Chun-Hsiang, Lu, Kun-Yen, Huang, Yu-Lien, Tsai, Ming-Huan
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/142,435
• Publication Number:
  US 20150187571A1
• Time in Patent Office: 655 Days
• Field of Search: 438/300, 438/424, 257/401, 257/E21.619
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched.

Claims

1. A method comprising:

forming isolation regions in a semiconductor substrate;

forming a first semiconductor strip between opposite portions of isolation regions;

forming a second semiconductor strip overlying and contacting the first semiconductor strip;

performing a first recessing to recess the isolation regions, wherein a portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin;

performing a second recessing to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing; and

etching the inter-diffusion region.

2. The method of claim 1, wherein after the etching the inter-diffusion region, a portion of the semiconductor fin has a necking portion narrower than overlying portions of the second semiconductor strip and underlying portions of the first semiconductor strip.

3. The method of claim 2, wherein the necking portion is overlying an interface between the first semiconductor strip and the second semiconductor strip.

4. The method of claim 2, wherein the necking portion is underlying an interface between the first semiconductor strip and the second semiconductor strip, and wherein the necking portion is over top surfaces of a nearest portion of the isolation regions.

5. The method of claim 1 further comprising:

forming a dummy gate stack over the semiconductor fin;

forming source and drain regions on opposite sides of the dummy gate stack; and

after the forming the source and drain regions, removing the dummy gate stack, wherein the second recessing is performed after the removing the dummy gate stack.

6. The method of claim 1 further comprising, after the etching the inter-diffusion region, forming a replacement gate on a top surface and sidewalls of the semiconductor fin.

7. The method of claim 1 further comprising, before the etching the inter-diffusion region, performing an anneal to enlarge the inter-diffusion region.

8. A method comprising:

forming Shallow Trench Isolation (STI) regions in a semiconductor substrate, with a portion of the semiconductor substrate between opposite portions of the STI regions acting as a first semiconductor strip;

recessing a portion of the first semiconductor strip to form a first recess;

performing an epitaxy to grow a second semiconductor strip in the recess, wherein the second semiconductor strip contacts the first semiconductor strip;

performing a first recessing to recess the STI regions, wherein a portion of the second semiconductor strip is over top surfaces of the recessed STI regions, and forms a semiconductor fin;

forming a dummy gate stack to cover a middle portion of the semiconductor fin;

forming source and drain regions on opposite sides of the middle portion of the semiconductor fin;

forming an Inter-Layer Dielectric (ILD) to cover the source and drain regions;

removing the dummy gate stack to form a second recess, wherein the middle portion of the semiconductor fin is exposed to the second recess;

performing a second recessing to recess the STI regions;

etching an inter-diffusion region of the first semiconductor strip and the second semiconductor strip through the second recess; and

forming a gate dielectric and a gate electrode in the second recess, wherein the gate dielectric and the gate electrode are over the middle portion of the semiconductor fin.

9. The method of claim 8 further comprising, after the removing the dummy gate stack and before the second recessing, performing an annealing on the first semiconductor strip and the second semiconductor strip.

10. The method of claim 8, wherein the epitaxy comprises growing the second semiconductor strip to have a germanium atomic percentage higher than an atomic percentage of the first semiconductor strip.

11. The method of claim 8, wherein after the etching the inter-diffusion region, a portion of the semiconductor fin has a necking portion narrower than overlying portions of the second semiconductor strip and underlying portions of the first semiconductor strip.

12. The method of claim 11, wherein the necking portion is overlying an interface between the first semiconductor strip and the second semiconductor strip.

13. The method of claim 11, wherein the necking portion is underlying an interface between the first semiconductor strip and the second semiconductor strip, and wherein the necking portion is over top surfaces of a nearest portion of the STI regions.

14. The method of claim 11, wherein the etching the inter-diffusion region is performed using an etchant having an etching rate of germanium lower than an etching rate of silicon.

15. A method comprising:

forming a first semiconductor strip between opposite portions of Shallow Trench Isolation (STI) regions;

forming a second semiconductor strip overlapping and contacting the first semiconductor strip, with edges of the second semiconductor strip aligned to respective edges of the first semiconductor strip;

etching an inter-diffusion region of the first semiconductor strip and the second semiconductor strip, wherein an interface region of the first semiconductor strip and the second semiconductor strip is thinned to be narrower than an underlying portion of the first semiconductor strip and an overlying portion of the second semiconductor strip;

forming a gate dielectric extending on sidewalls of the first semiconductor strip and the second semiconductor strip; and

forming a gate electrode over the gate dielectric.

16. The method of claim 15 further comprising:

forming a dummy gate over the second semiconductor strip; and

removing the dummy gate to form a recess, with the second semiconductor strip exposed to the recess, wherein the inter-diffusion region is etched from the recess.

17. The method of claim 16, wherein after the removing the dummy gate, the inter-diffusion region has at least a portion in the STI regions, and the method further comprises recessing the STI regions to expose the inter-diffusion region.

18. The method of claim 15 further comprising, before the etching the inter-diffusion region, performing an anneal to enlarge the inter-diffusion region.

19. The method of claim 15, wherein the second semiconductor strip has a germanium atomic percentage higher than a germanium atomic percentage of the first semiconductor strip, and wherein the inter-diffusion region is etched using an etchant having a germanium etching rate lower than a silicon etching rate.

20. The method of claim 15 further comprising forming source and drain regions on opposite ends of the second semiconductor strip before the etching the inter-diffusion region.