Device and method for reducing contact resistance of a metal

• US 9,159,666 B2
• Filed: 05/23/2014
• Issued: 10/13/2015
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Ya-Lien, Su, Hung-Wen, Lin, Yu-Hung, Lee, Kuei-Pin, Chang, Yu-Min
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US14/286,859
• Publication Number:
  US 20140332962A1
• Time in Patent Office: 508 Days
• Field of Search: 257/751, 257/E23.09, 257/E21.579, 257/E21.584, 257/774, 257/773, 257/758, 438/653
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure for an integrated circuit includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N₂ flow at least 20 sccm.

Claims

1. A structure for an integrated circuit, the structure comprising:

a substrate;

a cap layer deposited on the substrate;

a dielectric layer deposited on the cap layer; and

a trench embedded in the dielectric layer, wherein the trench includes;

a TaN layer formed on a side wall of the trench, wherein the TaN layer has a greater concentration of nitrogen than tantalum;

a Ta layer formed over the TaN layer; and

a Cu-containing layer formed over the Ta layer, wherein an overall carbon (C) concentration of the TaN layer and the Ta layer is lower than about 0.2 percent (%).

2. The structure of claim 1, wherein an overall N/Ta ratio of the TaN layer and the Ta layer ranges from about 0.6 to about 1.0.

3. The structure of claim 1, wherein a N/Ta ratio of the TaN layer ranges from about 2.3 to about 2.6.

4. The structure of claim 1, further comprising a via integrated into the trench at a bottom portion of the trench, wherein the via reaches to the cap layer.

5. The structure of claim 4, wherein the trench has a CD about 0.045 μ

m and a contact resistance (Rc) of the structure has a standard deviation (σ

) less than about 0.4 Ohms (Ω

).

6. The structure of claim 1, wherein a thickness of the TaN layer ranges from about 10 to about 20 angstrom (Å

).

7. The structure of claim 1, wherein a thickness of the Ta layer ranges from about 50 to about 100 angstrom (Å

).

8. The structure of claim 1, wherein the TaN layer and the Ta layer comprise α

-Ta but substantially no β

-Ta.

9. A structure for an integrated circuit, the structure comprising:

a substrate;

a first cap layer formed over the substrate;

a first dielectric layer formed over the first cap layer;

a first trench embedded in the first dielectric layer, wherein the first trench includes;

a first TaN layer deposited on bottom and sidewalls of the first trench, wherein the first TaN layer has a greater concentration of nitrogen than tantalum;

a first Ta layer deposited over the first TaN layer; and

a first Cu-containing layer formed over the first Ta layer;

a second cap layer formed over the first dielectric layer;

a second dielectric layer formed over the second cap layer;

a second trench embedded in the second dielectric layer, wherein the second trench includes;

a second TaN layer deposited on bottom and sidewalls of the second trench, wherein the second TaN layer has a greater concentration of nitrogen than tantalum;

a second Ta layer deposited over the second TaN layer; and

a second Cu-containing layer formed over the second Ta layer; and

a via located between the first trench and the second trench, wherein the via is integrated into the first trench at a top portion of the first trench and integrated into the second trench at a bottom portion of the second trench.

10. The structure of claim 9, wherein a contact resistance (Rc) of the first trench to the second trench has a standard deviation (σ

) less than about 0.4 Ohms (Ω

).

11. The structure of claim 9, wherein a contact resistance (Rc) of the first trench to the second trench ranges from about 6 to about 11 Ohms (Ω

) while a critical dimension (CD) of the first trench ranges from about 0.05 to about 0.5 micrometer (μ

m).

12. The structure of claim 9, wherein a CD of the via ranges from about 0.025 to about 0.040 μ

m while a CD of the first trench or the second trench ranges from about 0.036 μ

m to about 1.0 μ

m.

13. The structure of claim 9, wherein a CD of the via ranges from about 0.040 to about 0.055 μ

m while a CD of the first trench or the second trench ranges from about 0.045 μ

m to about 1.0 μ

m.

14. The structure of claim 9, wherein a CD of the via ranges from about 0.055 to about 0.070 μ

m while a CD of the first trench or the second trench ranges from about 0.064 μ

m to about 1.0 μ

m.

15. A structure for an integrated circuit, the structure comprising:

a cap layer on a substrate;

a dielectric layer on the cap layer; and

a trench in the dielectric layer, the trench including a first barrier layer on bottom and sidewalls of the trench deposited with physical vapor deposition (PVD) of TaN, a second barrier layer on the first barrier layer using PVD of Ta, and a metal layer over the second barrier layer.

16. The structure of claim 15, wherein an overall N/Ta ratio of the TaN layer and the Ta layer ranges from about 0.6 to about 1.0.

17. The structure of claim 16, wherein a N/Ta ratio of the TaN layer ranges from about 2.3 to about 2.6.

18. The structure of claim 15, wherein the first barrier layer has a thickness ranging from about 10 to about 20 angstrom (Å

).

19. The structure of claim 15, wherein the second barrier has a thickness ranging from about 50 to about 100 Å

.

20. The structure of claim 15, further comprising a via integrated into the trench at a bottom portion of the trench, wherein the via reaches to the cap layer.