Millimeter wave wafer level chip scale packaging (WLCSP) device and related method

• US 9,159,692 B2
• Filed: 10/21/2014
• Issued: 10/13/2015
• Est. Priority Date: 02/21/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ding, Hanyi, Graf, Richard S., Hill, Gary R., Woods, Wayne H. Jr.
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/519,590
• Publication Number:
  US 20150037913A1
• Time in Patent Office: 357 Days
• Field of Search: 257690-693, 257/737, 257/780, 257/E23.021, 257/E23.068, 438/612, 438/613
• US Class Current: 1/1
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1713 Square or rectangular array
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H05K 1/0251 : related to vias or transitions between vias and transmission lines

Abstract

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Claims

1. A method of tuning a wafer level chip scale package (WLCSP) structure, the method comprising:

providing the WLCSP structure including;

a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane, wherein the PCB ground plane includes an opening;

a set of ground contact devices each contacting the printed circuit board trace connection;

a set of chip pads contacting each of the ground contact devices in the set of contact devices;

a chip ground plane connecting the set of chip pads, the chip ground plane including an opening; and

a signal interconnect interposed between two of the set of ground contact devices, the signal interconnect including;

a signal trace connection electrically isolated from the PCB ground plane;

a signal contact device contacting the signal trace connection;

a chip pad contacting the signal contact device; and

a signal trace connection on a chip contacting the chip pad;

determining a performance parameter of the WLCSP structure;

tuning a size of at least one of the opening in the PCB ground plane or the opening in the chip ground plane based upon the determined performance parameter; and

modifying a size of the signal contact device and the ground contact devices based upon the determined performance parameter.

2. The method of claim 1, wherein the set of ground contact devices includes at least one of a set of solder balls or a set of pillars.

3. The method of claim 1, wherein the signal contact device includes at least one of a solder ball or a pillar.

4. The method of claim 1, wherein the tuning includes at least one of:

determining a distance between at least two ground contact devices in the set of ground contact devices;

determining a dimension of at least one ground contact device in the set of ground contact devices;

determining a size of at least one chip pad in the set of chip pads;

determining a size of at least one of the signal trace connection electrically isolated from the PCB ground plane or the signal trace connection on the chip contacting the chip pad;

or determining a size of at least one of the opening in the PCB ground plane or the opening in the chip ground plane.