Active matrix emissive micro LED display

• US 9,159,700 B2
• Filed: 03/15/2013
• Issued: 10/13/2015
• Est. Priority Date: 12/10/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Sakariya, Kapil V., Bibl, Andreas, Hu, Hsin-Hua
• Primary Examiner(s): Sun, Yu-Hsi D
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US13/842,721
• Publication Number:
  US 20140159067A1
• Time in Patent Office: 942 Days
• Field of Search: 257/88
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/29118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/75281 in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• CPC Class Codes: H01L 2224/75282 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/75725 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 2224/83193 wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8381 involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/83825 Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 33/06 : within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/38 : with a particular shape
• CPC Class Codes: H01L 33/42 : Transparent materials
• CPC Class Codes: H01L 33/54 : having a particular shape
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.

Claims

1. An active matrix display panel comprising:

a thin film transistor (TFT) substrate including a pixel area and a non-pixel area, wherein the pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings;

a ground line in the non-pixel area;

an array of micro LED devices on the array of bottom electrodes within the corresponding array of bank openings; and

an array of top electrode layers electrically connecting the array of micro LED devices to the ground line;

wherein each micro LED device is a vertical micro LED device with a maximum width of 1 μ

m-100 μ

m.

2. The display panel of claim 1, wherein the ground line is a ground ring in the non-pixel area around the pixel area.

3. The display panel of claim 2, wherein the array of top electrode layers are electrically connected to the ground ring on opposite sides of the pixel area.

4. The display panel of claim 3, wherein each top electrode layer spans over a single row of micro LED devices.

5. The display panel of claim 3, wherein each top electrode layer spans over a plurality of rows of micro LED devices.

6. The display panel of claim 1, wherein the pixel area is not completely covered by the array of top electrode layers.

7. The display panel of claim 1, wherein the array of bottom electrodes are formed on sidewalls of the corresponding array of bank openings.

8. The display panel of claim 7, wherein the array of bottom electrodes are reflective to the visible wavelength range.

9. The display panel of claim 1, further comprising a patterned insulator layer covering the array of bottom electrodes, and an array of openings in the patterned insulator layer exposing the array of bottom electrodes.

10. The display panel of claim 9, wherein the patterned insulator layer covers edges of the array of bottom electrodes.

11. The display panel of claim 1, further comprising a transparent passivation layer spanning sidewalls of the array of micro LED devices within the array of bank openings, wherein the transparent passivation layer does not completely cover a top conductive contact of each micro LED device.

12. The display panel of claim 1, wherein the array of top electrode layers are formed of a transparent or semi-transparent material.

13. The display panel of claim 12, wherein the array of top electrode layers comprise a material selected from the group consisting of PEDOT and ITO.

14. The display panel of claim 1, wherein each vertical micro LED device comprises an inorganic semiconductor-based p-n diode.

15. The display panel of claim 14, wherein each vertical micro LED device includes a corresponding bottom conductive contact with a maximum width of 1 μ

m-100 μ

m.

16. The display panel of claim 15, wherein the corresponding bottom conductive contact of each vertical micro LED device is bonded to a corresponding bottom electrode.

17. The display panel of claim 16, wherein each bottom electrode is independently addressable.

18. The display panel of claim 16, wherein each vertical micro LED device has a maximum width of 1 μ

m-20 μ

m.