Architecture to improve cell size for compact array of split gate flash cell with buried common source structure
First Claim
1. A memory device comprising:
- a first pair of split gate flash memory cells residing within a first active region, the first active region having an upper surface in a semiconductor body, wherein the first pair of split gate flash memory cells share a first shared erase gate having a dish shaped surface that extends below the upper surface of the first active region;
a first shared common source region disposed below the dish shaped surface of the first erase gate in the first active region;
a second pair of split gate flash memory cells residing within a second active region, the second active region having an upper surface in the semiconductor body, wherein the second pair of split gate flash memory cells share a second shared erase gate having a dish shaped surface that extends below the upper surface of the second active region;
a second shared common source region disposed below the dish shaped surface of the second erase gate in the second active region;
an isolation region disposed within a trench in the semiconductor body separating the first and second active regions; and
a buried doped conductive path disposed beneath the isolation region extending between the first and second shared common source regions, wherein the buried doped conductive path has an undulating shape, following an inner profile of the trench.
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Abstract
Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.
24 Citations
20 Claims
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1. A memory device comprising:
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a first pair of split gate flash memory cells residing within a first active region, the first active region having an upper surface in a semiconductor body, wherein the first pair of split gate flash memory cells share a first shared erase gate having a dish shaped surface that extends below the upper surface of the first active region; a first shared common source region disposed below the dish shaped surface of the first erase gate in the first active region; a second pair of split gate flash memory cells residing within a second active region, the second active region having an upper surface in the semiconductor body, wherein the second pair of split gate flash memory cells share a second shared erase gate having a dish shaped surface that extends below the upper surface of the second active region; a second shared common source region disposed below the dish shaped surface of the second erase gate in the second active region; an isolation region disposed within a trench in the semiconductor body separating the first and second active regions; and a buried doped conductive path disposed beneath the isolation region extending between the first and second shared common source regions, wherein the buried doped conductive path has an undulating shape, following an inner profile of the trench. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory device disposed on a semiconductor substrate comprising:
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a first pair of split gate flash memory cells residing within a first active region, having a first shared common source region disposed below a dish shaped surface in the first active region; and a second pair of split gate flash memory cells residing within a second active region, having a second shared common source region disposed below a dish shaped surface in the second active region, wherein the second pair of split gate flash memory cells is isolated from the first pair of split gate flash memory cells by a shallow trench isolation region; wherein the first shared common source region and the second shared common source region are connected by a buried conductive path which has an undulating shape and is disposed under the shallow trench isolation (STI) region. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A split gate flash memory device, comprising:
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a first pair of split gate flash memory cells which are disposed over an upper surface of a semiconductor body, wherein the upper surface of the semiconductor body exhibits a first recessed region which is arranged between the first pair of split gate flash cells and which extends below the upper surface of the semiconductor body; a first common source region which is disposed in the first recessed region of the semiconductor body below the upper surface of the semiconductor body and which is common to first pair of split gate flash memory cells; an erase gate which is disposed over the first recessed region and which has a dish-shaped lower surface that extends below the upper surface of the semiconductor body; a conformal dielectric layer disposed in the first recessed region of the semiconductor body and separating the first common source region from the erase gate; a second pair of split gate flash memory cells spaced laterally apart from the first pair of split gate flash memory cells and a second recessed region arranged between the second pair of split gate flash cells; a second common source region disposed in the second recessed region of the semiconductor body below the upper surface of the semiconductor body; a conductive path disposed in the semiconductor body electrically connecting the first and second common source regions, the conductive path having an undulating shape along a direction which is perpendicular to an orientation of split gate flash memory cells of each pair; and an isolation region disposed within a trench in the semiconductor body and separating active regions of the first and second pairs of split gate flash memory cells; wherein the conductive path extends beneath the isolation region to couple the first and second common source regions to one another. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification