Data line arrangement and pillar arrangement in apparatuses

• US 9,159,736 B2
• Filed: 02/07/2014
• Issued: 10/13/2015
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Vu, Luyen, Helm, Mark A.
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US14/175,901
• Publication Number:
  US 20150228659A1
• Time in Patent Office: 613 Days
• Field of Search: 257/66, 257/329
• US Class Current: 1/1
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

Claims

1. An apparatus, comprising a plurality of semiconductor pillars in a substantially hexagonally closest packed arrangement;

the hexagonally closest packed arrangement comprising a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different pillars, wherein each of the different pillars in a respective one of the repeating pillar patterns is electrically coupled to a different data line of a plurality of data lines; and

wherein each of the pillars in a respective one of the repeating pillar patterns is encompassed by a single drain-side select gate (SGD).

2. The apparatus of claim 1, wherein said each of the pillars in a respective one of the repeating pillar patterns being encompassed by a single drain-side select gate (SGD) comprises each of the pillars in the respective one of the repeating pillar patterns being at least partially surrounded by the single SGD, and wherein activation of the single SGD electrically couples the 7 different pillars to 7 different data lines.

3. The apparatus of claim 2, wherein a drain-side select gate (SGD) pitch as at least four-fold larger than a pitch of the data lines.

4. The apparatus of claim 2, wherein the drain-side select gate (SGD) comprises a common gate conductor for a plurality of SGD devices.

5. The apparatus of claim 1, wherein the data lines comprise bitlines.

6. The apparatus of claim 1, wherein the pillars are substantially vertical.

7. The apparatus of claim 1, wherein additional data lines are above the repeating pillar pattern and are not connected to any of the 7 pillars of the repeating pillar pattern.

8. An apparatus, comprising a plurality of semiconductor pillars in a substantially hexagonally closest packed arrangement;

the hexagonally closest packed arrangement comprising a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different pillars, wherein all 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

9. The apparatus of claim 8, wherein the pillars are substantially vertical.

10. The apparatus of claim 9, wherein the pillars comprise polysilicon.

11. The apparatus of claim 9, wherein the pillars comprise polysilicon at least partially surrounding a dielectric material.

12. The apparatus of claim 11, wherein the dielectric material comprises silicon dioxide.

13. The apparatus of claim 8, wherein the pillars are on a first pitch, and wherein the drain-side select gate (SGD) is one of a plurality of SGDs on a second pitch which is at least double the first pitch.

14. The apparatus of claim 8, wherein additional pillars are encompassed by the SGD and are not part of the repeating hexagonal pattern.

15. The apparatus of claim 8, wherein the SGD is separated from the pillars by gate dielectric.

17. The apparatus of claim 15, wherein the data lines are on a pitch of less than or equal to about 52 nanometers and wherein the SGDs are on a pitch of greater than or equal to about 423 nanometers.

18. The apparatus of claim 15, wherein the data lines are on a pitch of less than or equal to about 38 nanometers and wherein the SGDs are on a pitch of greater than or equal to about 577 nanometers.

19. The apparatus of claim 15, wherein additional data lines are above the repeating pillar pattern and are not connected to any of the 7 pillars of the repeating pillar pattern.

20. The apparatus of claim 15, wherein additional pillars are encompassed by the SGD and are not part of the repeating hexagonal pattern.

21. The apparatus of claim 15, wherein the pillars are substantially vertical and are comprised by vertically-stacked memory cells.

22. The apparatus of claim 20, wherein the memory cells are comprised by a NAND arrangement.

16. An apparatus, comprising a plurality of semiconductor pillars in a substantially hexagonally closest packed arrangement;

the hexagonally closest packed arrangement comprising a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different pillars, wherein each of the different pillars in a respective one of the repeating pillar patterns is electrically coupled to a different data line of a plurality of data lines;

wherein the data lines are on a pitch of less than or equal to about 60 nanometers;

wherein each of the pillars in a respective one of the repeating pillar patterns is encompassed by a single drain-side select gate (SGD) of a plurality of SGDs, and wherein the SGDs are on a pitch of greater than or equal to about 400 nanometers.