Method for protecting a semiconductor device against degradation and a method for manufacturing a semiconductor device protected against hot charge carriers

• US 9,159,796 B2
• Filed: 11/19/2013
• Issued: 10/13/2015
• Est. Priority Date: 07/26/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Mauder, Anton, Schulze, Hans-Joachim
• Primary Examiner(s): ULLAH, ELIAS
• Application Number:
  US14/083,595
• Publication Number:
  US 20140070356A1
• Time in Patent Office: 693 Days
• Field of Search: 438/268, 257/328, 257/546, 257/E21.41
• US Class Current: 1/1
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided.

Claims

1. A method for protecting a semiconductor device against degradation of its electrical characteristics, comprising:

providing a semiconductor device comprising a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface, the first semiconductor region comprising majority charge carriers of a first charge type, and the charged dielectric layer comprising fixed charges of the first charge type; and

configuring a charge carrier density per area of the fixed charges such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region.

2. The method of claim 1, further comprising providing the semiconductor device with the charged dielectric layer being arranged along a drift region formed by the first semiconductor region.

3. The method of claim 1, further comprising providing the semiconductor device with the charged dielectric layer forming at least a part of a field dielectric layer which insulates a field plate from the first semiconductor region.

4. The method of claim 1, wherein the charge carrier density per area of the fixed charges changes step-wise or continuously along a path in the charged dielectric layer, the path being parallel to the dielectric-semiconductor interface.

5. The method of claim 1, wherein the charged dielectric layer comprises a maximum carrier density per area of the fixed charges which is larger than about 10¹¹/cm².

6. A method for forming a semiconductor device, comprising:

providing a semiconductor body comprising a first semiconductor region comprising majority charge carriers of a first charge type;

forming a dielectric region comprising fixed charges of the first charge type, comprising;

forming a first dielectric layer on the first semiconductor region;

forming a second layer on the first dielectric layer by atomic layer deposition; and

forming a second dielectric layer on the second layer, such that the dielectric region and the first semiconductor region form an insulator-semiconductor interface; and

forming an electrode structure next to the dielectric region, such that the electrode structure is insulated from the semiconductor body;

wherein the first semiconductor region forms a drift region, and wherein the electrode structure forms at least one of a field plate and a gate electrode comprising a portion which is arranged next to the dielectric region and configured to operate as a field plate.

7. The method of claim 6, wherein the dielectric region is formed such that the dielectric region comprises portions of different maximum charge carrier densities per area.

8. The method of claim 6, wherein the first dielectric layer comprises silicon oxide, and wherein the second layer comprises at least one of aluminum, aluminum oxide, cesium, cesium oxide, and a nitride doped silicon oxide.

9. The method of claim 6, wherein forming a first dielectric layer comprises at least one of:

depositing a semiconductor material;

thermally oxidizing; and

depositing a dielectric material.