Electronic device comprising conductive structures and an insulating layer between the conductive structures and within a trench

• US 9,159,797 B2
• Filed: 12/13/2013
• Issued: 10/13/2015
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Loechelt, Gary H., Venkatraman, Prasad
• Primary Examiner(s): Diallo, Mamadou
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US14/106,504
• Publication Number:
  US 20140103424A1
• Time in Patent Office: 669 Days
• Field of Search: 257/288, 257/329, 257/330, 257/341, 257/328, 257/E21.409, 257/E29.255, 257/E29.262, 438/299, 438/197, 438/268, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow R_DSON to be lower for a given BV_DSS.

Claims

1. An electronic device comprising:

a substrate including an underlying doped region;

a semiconductor layer overlying the substrate, wherein;

the semiconductor layer has a primary surface opposite the underlying doped region; and

a trench has sidewalls and extends at least partly through the semiconductor layer;

a first conductive structure adjacent and electrically connected to the underlying doped region;

an insulating layer within the trench; and

a second conductive structure within the trench,

wherein, in a direction normal to the primary surface;

the insulating layer is disposed between the first and second conductive structures;

the first conductive structure is disposed at a location below the insulating layer and above the underlying doped region.

2. The electronic device of claim 1, wherein the first conductive structure comprises a conductive fill material and is disposed within the trench.

3. The electronic device of claim 2, wherein the trench extends to the underlying doped region.

4. The electronic device of claim 1, wherein the first conductive structure includes a heavily doped portion of the semiconductor layer disposed below the trench, wherein the first conductive structure underlies and generally corresponds to the trench.

5. The electronic device of claim 1, wherein the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, wherein:

the first semiconductor layer is adjacent to the underlying doped region and has a first dopant concentration; and

the second semiconductor layer is adjacent to the primary surface and is undoped or has a second dopant concentration less than the first dopant concentration.

6. The electronic device of claim 5, wherein each of the first and second semiconductor layers is at least approximately 1.1 microns thick.

7. The electronic device of claim 5, wherein the first semiconductor layer has a dopant concentration in a range of approximately 2×

10¹⁷ atoms/cm³ to approximately 5×

10¹⁸ atoms/cm³.

8. The electronic device of claim 1, further comprising a vertically-oriented doped region adjacent to a sidewall of the trench, wherein the vertically-oriented doped region is electrically insulated from the second conductive structure.

9. The electronic device of claim 8, wherein the vertically-oriented doped region has a peak dopant concentration in a range of approximately 5×

10¹⁶ atoms/cm³ to approximately 5×

10¹⁸ atoms/cm³.

10. The electronic device of claim 1, further comprising a gate electrode, wherein substantially all of the gate electrode overlies the primary surface.

11. An electronic device comprising:

a substrate including an underlying doped region;

a semiconductor layer overlying the substrate, wherein;

the semiconductor layer has a primary surface opposite the underlying doped region; and

a trench has sidewalls and extends at least partly through the semiconductor layer;

a first conductive structure adjacent to the underlying doped region;

an insulating layer within the trench; and

a second conductive structure within the trench,

wherein;

the insulating layer is disposed between the first and second conductive structures;

in a direction normal to the primary surface, the first conductive structure is disposed between the insulating layer and the underlying doped region; and

a vertical centerline of the trench intersects both the first and second conductive structures.

12. The electronic device of claim 11, wherein the first conductive structure lies along a conduction path within a drain region of a transistor structure.

13. The electronic device of claim 12, further comprising a gate electrode of the transistor structure, wherein the gate electrode overlies the primary surface.

14. The electronic device of claim 13, further comprising a source region of the transistor structure, wherein the source region is adjacent to the primary surface.

15. The electronic device of claim 14, wherein the source region and the second conductive structure are electrically connected to each other.

16. The electronic device of claim 13, further comprising a vertically-oriented doped region along a sidewall of the trench, wherein the vertically-oriented doped region has a peak dopant concentration in a range of approximately 2×

10¹⁷ atoms/cm³ to approximately 5×

10¹⁸ atoms/cm³.

17. An electronic device comprising:

a substrate including an underlying doped region;

a semiconductor layer overlying the substrate, wherein;

the semiconductor layer has a primary surface opposite the underlying doped region; and

a trench has sidewalls and extends at least partly through the semiconductor layer;

a transistor structure including;

a source region adjacent to the primary surface;

a gate electrode overlying the primary surface; and

a drain region that includes a first conductive structure extending from the trench toward the underlying doped region;

an insulating layer within the trench; and

a second conductive structure within the trench, wherein, as viewed from a top view, the insulating layer is disposed at a location above the first conductive structure and below the second conductive structure.

18. The electronic device of claim 17, further comprising a deep body region, wherein:

the transistor structure comprises a channel doped region; and

from a top view, the deep body region lies directly below and contacts the channel doped region.

19. The electronic device of claim 17, further comprising a vertically-oriented doped region along a sidewall of the trench.

20. The electronic device of claim 19, wherein the vertically-oriented doped region and the first conductive structure are parts of the drain region of the transistor structure.