Replacement gate process and device manufactured using the same

• US 9,159,798 B2
• Filed: 05/03/2013
• Issued: 10/13/2015
• Est. Priority Date: 05/03/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wang, Jun-Jie, Tsao, Po-Chao, Liang, Chia-Jui, Tzou, Shih-Fang, Lin, Chien-Ting, Chen, Cheng-Guo, Fu, Ssu-I, Hung, Yu-Hsiang, Chang, Chung-Fu
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US13/886,382
• Publication Number:
  US 20140327055A1
• Time in Patent Office: 893 Days
• Field of Search: 438/197, 438/585, 257/288
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Claims

1. A replacement gate process, comprising:

providing a substrate, and a dummy gate structure formed on the substrate, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer, and an interlayer dielectric layer covering the CESL, wherein the spacers and the CESL are made of the same material;

planarizing the interlayer dielectric (ILD) layer to expose a top surface of the CESL and form a patterned ILD layer, wherein the top surface of the CESL covering the hard mask layer is aligned with a top surface of the patterned ILD layer;

dry etching the CESL for removing a top portion of the CESL by stopping at a top surface of the hard mask layer to expose the hard mask layer;

removing the hard mask layer; and

removing the dummy layer to form a trench.

2. The replacement gate process according to claim 1, wherein material of the HM layer is different from that of the spacers and the CESL.

3. The replacement gate process according to claim 1, wherein the dummy layer is a polysilicon layer, or amorphous silicon layer.

4. The replacement gate process according to claim 1, wherein the spacers and the CESL are made of SICN, which is formed by atomic layer deposition (ALD).

5. The replacement gate process according to claim 1, wherein the hard mask layer is made of nitrite or oxide.

6. The replacement gate process according to claim 5, wherein the hard mask layer is made of SIN.

7. The replacement gate process according to claim 1, wherein the hard mask layer is removed by wet etching.

8. The replacement gate process according to claim 1, wherein the dummy gate structure further comprises a gate dielectric layer between the substrate and the dummy layer.

9. The replacement gate process according to claim 8, wherein the gate dielectric layer is a high-K dielectric layer, or a multi-layer comprising an oxide layer and the high-K dielectric layer formed on the oxide layer.

10. The replacement gate process according to claim 1, further comprising forming a gate dielectric layer in the trench.

11. The replacement gate process according to claim 1, further comprising forming a metal gate in the trench.

12. The replacement gate process according to claim 1, wherein a fin channel is formed on the substrate, and the dummy gate structure is formed on the fin channel and the substrate by exposing a portion of the fin channel, and a source and a drain are separately formed on two oppositely sides of the exposed portion of the fin channel adjacent to the dummy gate structure.

13. The replacement gate process according to claim 1, wherein a thickness of the dummy layer is in a range of 400 Å

to 1200 Å

.