Vertical gate LDMOS device

• US 9,159,804 B2
• Filed: 09/16/2014
• Issued: 10/13/2015
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Volterra Semiconductor LLC (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor LLC (Analog Devices, Inc.)
• Inventors: Zuniga, Marco A., Lu, Yang, Fatemizadeh, Badredin, Prasad, Jayasimha, Paul, Amit, Ruan, Jun
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US14/487,574
• Publication Number:
  US 20140374826A1
• Time in Patent Office: 392 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

Claims

1. A transistor comprising:

an n-well region implanted into a surface of a substrate;

a trench in the n-well region, the trench having a first side and an opposing second side, the trench extending from the surface to a first depth, the trench comprising

a gate of conductive material in the trench, and

dielectric material filling a volume of the trench not filled by the conductive material;

a p-type material in a first region extending from a second depth to a third depth in the n-well region, wherein each of the second depth and the third depth is greater than the first depth;

a source region on the first side of the trench, the source region including a p-body region wherein an n+ region and a p+ region is implanted in the p-body region; and

a drain region on the second side of the trench, the drain region comprising an n+ region;

wherein the p+ region of the p-body is below the n+ region of the p-body.

2. The transistor of claim 1 further comprising a first source electrode in contact with the p+ region and a second source electrode in contact with the n+ region.

3. A transistor comprising:

an n-well region implanted into a surface of a substrate;

a trench in the n-well region, the trench having a first side and an opposing second side, the trench extending from the surface to a first depth, the trench comprising

a gate of conductive material in the trench, and

dielectric material filling a volume of the trench not filled by the conductive material;

a p-type material in a first region extending from a second depth to a third depth in the n-well region, wherein each of the second depth and the third depth is greater than the first depth;

a source region on the first side of the trench, the source region including a p-body region wherein an n+ region and a p+ region is implanted in the p-body region; and

a drain region on the second side of the trench, the drain region comprising an n+ region;

wherein the p-type material in the first region is a portion of an epitaxial layer.

4. The transistor of claim 3 further comprising a layer of n-type material between the epitaxial layer and the substrate.

5. A transistor comprising:

an n-well region implanted into a surface of a substrate;

a trench in the n-well region, the trench having a first side and an opposing second side, the trench extending from the surface to a first depth, the trench comprising

a gate of conductive material in the trench, and

dielectric material filling a volume of the trench not filled by the conductive material;

a p-type material in a first region extending from a second depth to a third depth in the n-well region, wherein each of the second depth and the third depth is greater than the first depth;

a source region on the first side of the trench, the source region including a p-body region wherein an n+ region and a p+ region is implanted in the p-body region; and

a drain region on the second side of the trench, the drain region comprising an n+ region;

wherein the p-type material in the first region is a portion of a reduced surface field (RESURF) layer.

6. The transistor of claim 5 further comprising a layer of n-type material between the RESURF layer and the substrate.

7. A method of fabricating a transistor, the method comprising:

implanting, into a surface of a substrate, an n-well region;

forming a trench in the n-well such that a length of the trench extends from the surface of the n-well region to a first depth in the n-well region and a width of the trench extends from a first side on the surface of the n-well to a second side on the surface on the n-well;

implanting a p-type material in a first region extending from a second depth to a third depth in the n-well, wherein the p-type material in implanted through a bottom of the trench at the first depth and each of the second depth and the third depth is greater than the first depth;

implanting an n-type material in a second region in the n-well such that the second region extends from the bottom of the trench to the first region, wherein the n-type material is implanted through the bottom of the trench at the first depth;

forming an asymmetric gate of conductive material in the trench such that a distance of the asymmetric gate from the first side of the trench is less than a distance of the asymmetric gate from the second side of the trench;

filling, by an oxide, a volume of the trench not covered by the asymmetric gate;

implanting, into a source region of the transistor, a p-body region such that the p-body region extends from the surface of the n-well to the first region, wherein the source region is at the first side of the trench;

implanting, into the source region of the transistor, an n+ region and a p+ region, in the p-body region; and

implanting, into a drain region of the transistor, an n+ region, wherein the drain region is at the second side of the trench.

8. The method of claim 7, wherein implanting the n type material in the second region is configured such that the second region has a lower concentration of p type material than the p-body.

9. The method of claim 8, further comprising substantially neutralizing the p type material in the second region by the implanted n type material.

10. The method of claim 7, wherein forming the trench further comprises:

depositing a masking layer on the n-well region;

patterning the masking layer to define a site for the trench; and

etching out a portion of the n-well region, at the site.

11. The method of claim 7, wherein the p-type material is implanted in the first region using an implant beam having an implant angle between 0-30 degree and an implant energy between 50-300 KeV.

12. The method of claim 7, wherein the n-type material is implanted in the second region using an implant beam having an implant angle between 0-30 degree and an implant energy between 50-250 KeV.

13. The method of claim 7, wherein forming the asymmetric gate further comprises oxidizing the trench to increase a thickness of the oxide at the bottom of the trench.

14. The method of claim 13, further comprising forming a layer of nitride on substantially vertical walls of the trench, the nitride layer configured to at least partially block oxidation of the walls.

15. The method of claim 7, wherein implanting the p-body region further comprises:

forming and pattering a masking layer to expose a region on the surface of the substrate through which the p-body region is formed;

implanting a deep p-body region using an implant beam having a first angle and a first energy; and

implanting a shallow p-body region using an implant beam having a second angle and a second energy, wherein the second angle is greater than the first angle and the second energy is less than the first energy.

16. The method of claim 15, wherein the shallow p-body has a higher resultant implant concentration than the deep p-body.

17. The method of claim 7 further comprising forming metallic contacts at the source, gate and drain regions.