Top drain LDMOS
First Claim
1. A top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate comprising:
- a source electrode disposed on a bottom surface of the semiconductor substrate;
a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate with gate sidewalls covered by a gate insulation spacer laterally extending away from the planar gate wherein the source region is encompassed in a body region contacting a drift region as a lateral current channel between the source region and drain region under the planar gate;
at least a body-source interconnect trench opened into the semiconductor substrate vertically aligned with an edge of the gate insulation spacer wherein the trench is filled with a conductive material having a top surface below the top surface of the semiconductor substrate for exposing a sidewall of the source region underneath the gate insulation spacer and extending vertically from the body region near the top surface of the semiconductor substrate downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate; and
a gate shield metal layer covering over the gate insulation spacer and extending laterally over the sidewall surface of the source region underneath the gate insulation spacer and covering a top surface of the body-source interconnect trench.
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Accused Products
Abstract
In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
18 Citations
14 Claims
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1. A top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate comprising:
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a source electrode disposed on a bottom surface of the semiconductor substrate; a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate with gate sidewalls covered by a gate insulation spacer laterally extending away from the planar gate wherein the source region is encompassed in a body region contacting a drift region as a lateral current channel between the source region and drain region under the planar gate; at least a body-source interconnect trench opened into the semiconductor substrate vertically aligned with an edge of the gate insulation spacer wherein the trench is filled with a conductive material having a top surface below the top surface of the semiconductor substrate for exposing a sidewall of the source region underneath the gate insulation spacer and extending vertically from the body region near the top surface of the semiconductor substrate downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate; and a gate shield metal layer covering over the gate insulation spacer and extending laterally over the sidewall surface of the source region underneath the gate insulation spacer and covering a top surface of the body-source interconnect trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor power device comprising:
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a gate disposed on a top surface of a semiconductor substrate for controlling a current path between a source region and a drain region disposed near the top surface of the substrate; a body-source interconnect trench filled with a conductive material comprising a heavily doped P++ selective epitaxial growth (SEG) of silicon-germanium (SiGe) and extends downwardly for shorting the source region to a source electrode disposed on a bottom surface of the substrate; and
wherein the heavily doped P++ selective epitaxial growth (SEG) of silicon-germanium (SiGe) having a top surface below the top surface of the semiconductor substrate for exposing a sidewall of the source region underneath the gate insulation spacer; anda gate shield metal layer covering over a gate insulation spacer and extending laterally over a sidewall surface of the source region underneath the gate insulation spacer and covering over a top surface of the body-source interconnect trench.
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Specification