Embedded nonvolatile memory

• US 9,159,842 B1
• Filed: 03/28/2014
• Issued: 10/13/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Wu, Wei-Cheng, Tseng, Yuan-Tai, Liu, Shih-Chang, Tsai, Chia-Shiung, Lee, Ru-Liang, Chuang, Harry Hak-Lay
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): FORTICH, RODOLFO D
• Application Number:
  US14/229,191
• Publication Number:
  US 20150280004A1
• Time in Patent Office: 564 Days
• Field of Search: 257/211, 257/314, 257/324, 257/326, 257/321
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/30 : characterised by the memory core region

Abstract

A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Claims

1. A method of forming a nonvolatile memory, the method comprising:

forming two gate stacks on a substrate, wherein the gate stacks each from bottom to top sequentially comprises a tunneling oxide layer, a floating gate, a middle dielectric layer, a control gate, and a mask layer;

forming first spacers on sidewalls of the two gate stacks;

forming a gate dielectric layer on an exposed portion of the substrate;

sequentially forming a polysilicon layer and an organic layer above the substrate, wherein the polysilicon layer has a thickness smaller than a total thickness of the tunneling oxide layer, the floating gate, the middle dielectric layer, and the control gates, as well as the organic layer has a top surface higher than top surfaces of the gate stacks;

etching the organic layer and the polysilicon layer until the top surface of the polysilicon layer is not higher than top surfaces of the control gates;

removing a residue of the organic layer;

forming a first dielectric layer above the substrate; and

anisotropically etched the first dielectric layer and the polysilicon layer thereunder until the substrate is exposed, wherein the polysilicon layer is etched to form an erase gate between the two gate stacks as well as word lines located on outer sides of the two gate stacks, and the first dielectric layer is etched to form first cap layers on the word lines and the erase gate.

2. The method of claim 1, wherein the first spacers each comprises an inner silicon oxide layer and an outer silicon nitride layer.

3. The method of claim 1, further comprising:

forming a second dielectric layer above the substrate; and

anisotropically etching the second dielectric layer until the substrate is exposed to form second spacers on outer sidewalls of the word lines.

4. The method of claim 1, further comprising:

forming a buffer layer between the polysilicon layer and the first dielectric layer.

5. The method of claim 1, wherein the word lines are formed by using the first cap layers as an etching mask.

6. The method of claim 1, wherein the first dielectric layer comprises a silicon nitride layer.

7. The method of claim 3, further comprising:

forming a buffer layer between the first dielectric layer and the second dielectric layer.

8. The method of claim 3, wherein the second dielectric layer comprises a silicon nitride layer.

9. The method of claim 1, further comprising:

forming a metal silicide layer in the substrate exposed by the two gate stacks, the first spacers, the erase gate, the word lines, and the first cap layers.

10. A method of forming a nonvolatile memory, the method comprising:

forming two gate stacks on a substrate, wherein the gate stacks each from bottom to top sequentially comprises a tunneling oxide layer, a floating gate, a middle dielectric layer, a control gate, and a mask layer;

forming first spacers on sidewalls of the two gate stacks;

forming a gate dielectric layer on a first exposed portion of the substrate;

sequentially forming a polysilicon layer and a first dielectric layer above the substrate, wherein the polysilicon layer has a thickness smaller than a total thickness of the tunneling oxide layer, the floating gate, the middle dielectric layer, and the control gates;

anisotropically etching the first dielectric layer and polysilicon layer thereunder until a second portion of substrate is exposed, wherein the polysilicon layer is etched to form an erase gate between the two gate stacks as well as word lines located on outer sides of the two gate stacks, and the first dielectric layer is etched to form first cap layers on the word lines and the erase gate;

forming an organic layer on the second exposed portion of the substrate;

etching the word lines and the erase gate until the erase gate and the word lines have top surfaces lower than top surfaces of the control gates;

removing the organic layer;

forming a second dielectric layer above the substrate; and

anisotropically etching the second dielectric layer to form second spacers on outer sidewalls of the word lines and second cap layers on the word lines and the erase gate.

11. The method of claim 10, wherein the first spacers each comprises an inner silicon oxide layer and an outer silicon nitride layer.

12. The method of claim 10, wherein the first dielectric layer and the second dielectric layer each comprises a bottom silicon oxide layer and a top silicon nitride layer.

13. The method of claim 10, wherein the etching of the word lines and the erase gate is performed by dry etching.

14. The method of claim 13, wherein the dry etching is performed in a poly etcher by using SF₆ as a plasma source.

15. The method of claim 13, wherein the dry etching is performed in a remote plasma etcher by using C_xH_yF_z and oxygen as a plasma source, and the C_xH_yF_z is CH₂F₂, CHF₃, CF₄, C₂F₆, C₃F₈, C₄F₆, or C₅F₈.

16. The method of claim 10, further comprising:

removing a portion of the organic layer to expose the word lines and the erase gate before etching the exposed word lines and the exposed erase gate.

17. The method of claim 10, further comprising:

forming a buffer layer between the first dielectric layer and the second dielectric layer.

18. The method of claim 10, further comprising:

forming a metal silicide layer in the substrate exposed by the two gate stacks, the first spacers, the erase gate, the word lines, the second spacers, the first cap layers, and the second cap layers.

19. The method of claim 10, further comprising:

forming an etching stop layer on the second dielectric layer and the substrate.

20. The method of claim 19, further comprising:

forming a low-k dielectric layer on the etching stop layer, wherein a dielectric constant of the low-k dielectric layer is smaller than a dielectric constant of silicon dioxide.