Analog amplifiers and comparators

• US 9,160,293 B2
• Filed: 09/08/2014
• Issued: 10/13/2015
• Est. Priority Date: 09/07/2013
• Status: Active Grant

• Current Assignee: Likins J. Daniel, Robert C. Schober
• Original Assignee: Likins J. Daniel, Robert C. Schober
• Inventors: Schober, Robert C., Likins, J. Daniel
• Primary Examiner(s): Choe, Henry
• Application Number:
  US14/480,054
• Publication Number:
  US 20150070091A1
• Time in Patent Office: 400 Days
• Field of Search: 330/9, 330/51, 330/76, 330/207.A, 330/251
• US Class Current: 1/1
• CPC Class Codes: H03F 2200/153 Feedback used to stabilise the amplifier
• CPC Class Codes: H03F 2203/45101 Control of the DC level being present
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03G 1/0017 the device being at least one of the amplifying solid state elements of the amplifier

Abstract

An innovative analog circuit design using digital components is disclosed. Embodiments of the present invention includes, but not limited to analog amplifiers and comparators. An amplifier of an embodiment of the present invention includes an inverter, a plurality of switches, offset capacitor and flying capacitor. The one terminal of the offset capacitor is connected to the input of the inverter. During setup phase of clock signals, the switches are configured to connect input and output of the inverter and to connect the flying capacitor to input terminals of the amplifier, respectively, for storing a differential input voltage. Then, during the enable phase of the clock signals, the switches are configured to connect the first terminal of the second capacitor and the first terminal of the first capacitor, and to connect the second terminal of the second capacitor to the output of the inverter.

Claims

1. An amplifier comprising:

a. an inverter having an input and an output;

b. a plurality of switches operable with clock signals providing a setup phase and an enable phase;

c. a first capacitor, having a first terminal and a second terminal, and the second terminal of the first capacitor is in communication with the input of the inverter;

d. a second capacitor having a first terminal and a second terminal;

wherein

during the setup phase of the clock signals, the plurality of switches are configured to connect;

the input and the output of the inverter, and

the first and second terminals of the second capacitor to first and second input terminals of the amplifier, respectively, for storing a differential input voltage; and

during the enable phase of the clock signals, the plurality of switches are configured to connect;

the first terminal of the second capacitor and the first terminal of the first capacitor, and

the second terminal of the second capacitor to the output of the inverter.

2. An amplifier as in claim 1, wherein the clock signals are complementary and coincident clocks.

3. An amplifier as in claim 1, wherein the inverter is a CMOS inverter.

4. An amplifier as in claim 1, wherein the plurality of switches are transmission gates.

5. A sum or difference amplifier for first and second inputs, comprising:

an inverter having an input and an output;

a plurality of switches, operable by clock signals having setup and enable phases;

first, second and third capacitors, each having first and second terminals, the second terminal of the first capacitor is in communication with the input of the inverter;

wherein during the setup phase of the clock signals, the plurality of switches are configured to connect;

the input and the output of the inverter,

a output zero reference of the amplifier to the first terminal of the first capacitor,

a second input terminal of the first input of the amplifier to the second terminal of the second capacitor,

a first input terminal of the first input of the amplifier to the first terminal of the second capacitor,

a second input terminal of the second input of the amplifier to the second terminal of the third capacitor, and

a first input terminal of the second input of the amplifier to the first terminal of the third capacitor; and

during the setup phase of the clock signals, the plurality of switches are configured to connect;

the second terminal of the second terminal to an output terminal of the amplifier,

the first terminal of the second capacitor to the second terminal of the third capacitor, and

the first terminal of the third capacitor to the first terminal of the first capacitor.

6. A precision twice gain analog amplifier, comprising

an inverter having input and output;

an offset capacitor, and first and second capacitors, each having first and second terminals;

a plurality of switches operable by clock signals having setup and enable phases;

wherein the second terminal of the offset capacitor is connected to the input of the inverter;

wherein during the setup phase of the clock signals, the plurality of switches are configured to connect;

the input and the output of the inverter,

an output zero reference to the first terminal of the offset capacitor,

a second input terminal of the amplifier to the second terminal of the first capacitor,

the second input terminal of the amplifier to the second terminal of the second capacitor,

a first input terminal of the amplifier to the first terminal of the first capacitor, and

the first input terminal of the amplifier to the first terminal of the second capacitor; and

during the enable phase of the clock signals, the plurality of switches are configured to connect;

the second terminal of the first capacitor to an output terminal of the amplifier,

the first terminal of the first capacitor to the second terminal of the second capacitor, and

the first terminal of the second capacitor to the first terminal of the offset capacitor.

7. A precision twice gain analog amplifier as in claim 6, wherein capacitances of the first and second capacitors are different.

8. A comparator operative to compare the difference between a reference voltage at a reference terminal and an unknown input voltage at an input terminal, comprising:

an inverter having input and output;

a capacitor having first and second terminals, the second terminal of the capacitor is in communication with the input of the inverter, and

a plurality of switches operable by clock signals having setup and compare phases,

wherein during the setup phase of the clock signals, the plurality of switches are configured to connect the output and the input of the inverter, and a reference terminal of the comparator to the first terminal of the capacitor; and

during the compare phase of the clock signals, the plurality of switches are configured to connect an input terminal of the comparator to the first terminal of the capacitor.