Power efficient multiplexer

• US 9,160,321 B2
• Filed: 11/18/2013
• Issued: 10/13/2015
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert Paul
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US14/083,348
• Publication Number:
  US 20140070848A1
• Time in Patent Office: 694 Days
• Field of Search: 326/113, 326/119, 326/121, 326/122, 326/83, 327/415, 327/416, 327407-410
• US Class Current: 1/1
• CPC Class Codes: H03K 17/005 with several inputs only
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Claims

1. A method comprising:

outputting, from a latch circuit, at least one bit and a complement of the at least one bit;

selectively passing one of a plurality of input signals by using the at least one bit and the complement; and

independently of the at least one bit and the complement and a state of a clock signal, inverting an input signal from said selectively passing, wherein said inverting includes;

using a stacked inverter to invert the input signal from said selectively passing, wherein the stacked inverter comprises a low-to-high transition leg that includes a first number of transistors and a high-to-low transition leg that includes a second number of transistors that is different relative to the first number of transistors.

2. The method of claim 1, wherein said selectively passing comprises:

applying the at least one bit to a first transmission gate and a second transmission gate; and

applying the complement to the first transmission gate and the second transmission gate.

3. The method of claim 2, wherein said selectively passing further comprises:

if the at least one bit is a first value, outputting a first input signal from the first transmission gate.

4. The method of claim 3, wherein said selectively passing further comprises:

if the at least one bit is a second value, outputting a second input signal from the second transmission gate.

5. The method of claim 1, wherein the first number is greater than the second number.

6. The method of claim 1, wherein the first number is less than the second number.

7. A method comprising:

outputting, from a latch circuit, at least one bit and a complement of the at least one bit;

if the at least one bit is a first value, passing a first input signal by using the at least one bit and the complement;

if the at least one bit is a second value, passing a second input signal by using the at least one bit and the complement; and

independently of the at least one bit and the complement and a state of a clock signal, inverting an input signal from at least one of said passing a first input signal or said passing a second input signal, wherein said inverting includes;

using a stacked inverter to invert the input signal from at least one of said passing a first input signal or said passing a second input signal, wherein the stacked inverter comprises a low-to-high transition leg that includes a first number of transistors and a high-to-low transition leg that includes a second number of transistors that is different relative to the first number of transistors.

8. The method of claim 7, further comprising:

applying the at least one bit to a first transmission gate and a second transmission gate; and

applying the complement to the first transmission gate and the second transmission gate.

9. The method of claim 8, wherein said passing a first input signal comprises:

outputting the first input signal from the first transmission gate.

10. The method of claim 8, wherein said passing a second input signal comprises:

outputting the second input signal from the second transmission gate.

11. The method of claim 7, wherein the first number is greater than the second number.

12. The method of claim 7, wherein the first number is less than the second number.

13. A method comprising:

accessing a plurality of input signals;

outputting, from a latch circuit, at least one bit and a complement of the at least one bit;

using the at least one bit and the complement to select one of the plurality of input signals; and

independently of the at least one bit and the complement and a state of a clock signal, inverting an input signal from said using, wherein said inverting includes;

utilizing a stacked inverter to invert the input signal from said using, wherein the stacked inverter comprises a low-to-high transition leg that includes a first number of transistors and a high-to-low transition leg that includes a second number of transistors that is different relative to the first number of transistors.

14. The method of claim 13, wherein the first number is greater than the second number.

15. The method of claim 13, wherein the first number is less than the second number.