Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches

• US 9,160,328 B2
• Filed: 07/06/2013
• Issued: 10/13/2015
• Est. Priority Date: 07/07/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Altunkilic, Fikret, Blin, Guillaume Alexandre, Cebi, Haki, Fuh, Hanching, Hsu, Mengshu, Lee, Jong-Hoon, Madan, Anuj, Srirattana, Nuttapong, Shih, Chuming, Sprinkle, Steven Christopher
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): SKIBINSKI, THOMAS S
• Application Number:
  US13/936,180
• Publication Number:
  US 20140009214A1
• Time in Patent Office: 829 Days
• Field of Search: 327/534, 327/535, 327/537, 327/384, 327/427, 327/434, 327/437, 327308-311, 455/78
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.

Claims

1. A radio-frequency (RF) switch comprising:

first and second field-effect transistors (FETs) connected in series, each of the first and second FETs having a gate node and a body node;

a gate-coupling path that couples the gate node of the first FET to the gate node of the second FET, the gate-coupling path including a first capacitor having a first end coupled to the gate node of the first FET and a second end coupled to the gate node of the second FET;

a body-coupling path that couples the body node of the first FET to the body node of the second FET, the body-coupling path including a second capacitor having a first end coupled to the body node of the first FET and a second end coupled to the body node of the second FET; and

an adjustable-resistance circuit connected to the body nodes of the first and second FETs, the adjustable resistance circuit including a parallel combination of a first resistor and a bypass switch.

2. The switch of claim 1 wherein at least one of the first and second FETs is a silicon-on-insulator (SOI) FET.

3. The switch of claim 1 wherein the gate-coupling path further includes a second resistor in series with the first capacitor.

4. The switch of claim 1 wherein the gate-coupling path further includes a second resistor.

5. The switch of claim 3 wherein the body-coupling path further includes a third resistor in series with the second capacitor.

6. The switch of claim 1 wherein the body-coupling path further includes a second resistor.

7. The switch of claim 1 further comprising a switchable resistive coupling circuit connected to the gate nodes of the first and second FETs.

8. The switch of claim 1 further comprising a coupling circuit that couples the respective body and gate of each of the first and second FETs, the coupling circuit including a capacitor electrically parallel with a diode.

9. A semiconductor die comprising:

a semiconductor substrate;

first and second field-effect transistors (FETs) formed on the semiconductor substrate and connected in series, each of the first and second FETs including a gate node and a body node;

a gate-coupling path formed on the semiconductor substrate that couples the gate node of the first FET to the gate node of the second FET, the gate-coupling path including a first capacitor having a first end coupled to the gate node of the first FET and a second end coupled to the gate node of the second FET;

a body-coupling path formed on the semiconductor substrate that couples the body node of the first FET to the body node of the second FET, the body-coupling path including a second capacitor having a first end coupled to the body node of the first FET and a second end coupled to the body node of the second FET; and

an adjustable resistance circuit connected to the body nodes of the first and second FETs, the adjustable resistance circuit including a parallel combination of a resistor and a bypass switch.

10. The die of claim 9 further comprising an insulator layer disposed between the first and second FETs and the semiconductor substrate.

11. The die of claim 10 wherein the die is a silicon-on-insulator (SOI) die.

12. A method for fabricating a semiconductor die, the method comprising:

providing a semiconductor substrate;

forming first and second field-effect transistors (FETs) on the semiconductor substrate so as to be connected in series, each of the first and second FETs having a gate node and a body node;

forming a gate-coupling path on the semiconductor substrate to couple the gate node of the first FET to the gate node of the second FET, the gate-coupling path including a first capacitor having a first end coupled to the gate node of the first FET and a second end coupled to the gate node of the second FET;

forming a body-coupling path on the body node of the first FET to the body node of the second FET, the body-coupling path including a second capacitor having a first end coupled to the body node of the first FET and a second end coupled to the body node of the second FET;

connecting an adjustable-resistance circuit to the body nodes of the first and second FETs, the adjustable resistance circuit including a parallel combination of a resistor and a bypass switch.

13. The method of claim 12 further comprising forming an insulator layer between the first and second FETs and the semiconductor substrate.