Apparatus and method to update a default time interval based on process corner, temperature and voltage

• US 9,160,348 B2
• Filed: 11/23/2011
• Issued: 10/13/2015
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Jung, Hwisung
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Sampath, Gayathri
• Application Number:
  US13/303,922
• Publication Number:
  US 20130047012A1
• Time in Patent Office: 1,420 Days
• Field of Search: 713/320
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A processor arrangement changes its default time interval for entering a power saving mode based on sensed operating conditions and predetermined time intervals to be used under various operating conditions to optimize power saving.

Claims

1. A processor arrangement, comprising:

a processor configured to enter a power saving mode based on a default time interval;

a monitor configured to identify a process corner associated with the processor;

a memory storing a look-up table including respective time intervals associated with a plurality of operating parameters of the processor, the look-up table corresponding to the identified process corner, wherein each respective time interval stored in the look-up table is associated with a corresponding supply voltage and a corresponding temperature of the processor;

a sensor configured to sense a temperature of the processor; and

a power manager configured to;

select, based on the identified process corner and the temperature, an updated time interval from the look-up table, and

update the default time interval based on the updated time interval.

2. The processor arrangement of claim 1, wherein the sensor is further configured to sense a supply voltage of the processor.

3. The processor arrangement of claim 1, wherein the memory stores a plurality of look-up tables.

4. The processor arrangement of claim 3, wherein each look-up table in the plurality of look-up tables corresponds to a different potential process corner of a plurality of potential processor corners.

5. The processor arrangement of claim 1, wherein the power manager is further configured to:

compare the temperature to a previously sensed temperature, and

update the default time interval based on a result of the comparison.

6. A method, comprising:

identifying a process corner associated with a processor;

determining, during a first execution of a first application by the processor, a default time interval for the processor to enter into a power saving mode based on the process corner;

detecting a second execution of a second application by the processor;

detecting a change in temperature of the processor after detecting the second execution of the second application;

reading an updated default time interval from a look-up table corresponding to the process corner, wherein the look-up table includes respective time intervals associated with a plurality of operating parameters of the processor, and wherein each respective time interval stored in the look-up table is associated with a corresponding supply voltage and a corresponding temperature of the processor; and

updating the default time interval based on the updated default time interval.

7. The method of claim 6, further comprising:

detecting a change in supply voltage of the processor.

8. The method of claim 7, further comprising:

updating the default time interval based on the change in supply voltage.

9. The method of claim 6, further comprising:

selecting the look-up table from a plurality of look-up tables.

10. The method of claim 9, wherein each look-up table in the plurality of look-up tables corresponds to a different potential process corner of a plurality of potential process corners associated with the processor.

11. An apparatus, comprising:

a processor configured to enter a low power mode based on a time interval;

a memory storing a look-up table including respective durations of time associated with a plurality of operating parameters of the processor, wherein each respective duration of time stored in the look-up table is associated with a corresponding supply voltage and a corresponding temperature of the processor; and

a power manager coupled to the processor, wherein the power manager is configured to;

determine a process corner, within which the processor is operating, wherein the look-up table corresponds to the process corner,

determine a current operating condition of the processor,

select, based on the process corner and the current operating condition, a first duration of time from the look-up table, wherein the first duration of time is a duration of idle time to elapse before the processor enters the low power mode, and

update the time interval based on the first duration of time.

12. The apparatus of claim 11, wherein the current operating condition is a current temperature of the processor.

13. The apparatus of claim 11, wherein the current operating condition is a current supply voltage of the processor.

14. The apparatus of claim 11, wherein the power manager is further configured to:

determine a current temperature of the processor;

determine a current supply voltage of the processor; and

update time interval based on the current temperature, current supply voltage, and the process corner.

15. The apparatus of claim 11, wherein the low power mode is a dormant mode.

16. The apparatus of claim 11, further comprising:

a sensor configured to sense the current operating condition.

17. The apparatus of claim 11, further comprising:

a silicon performance monitor configured to identify the process corner, wherein the process corner is slow, typical, or fast.

18. The apparatus of claim 17, wherein the power manager is further configured to:

compare a reported count generated by the silicon performance monitor to a reference count associated with the process corner; and

select the first duration of time based on the reported count.

19. An apparatus, comprising:

a processor configured to enter a low power mode after a duration of idle time; and

a memory storing a plurality of look-up tables, each look-up table corresponding to a different potential process corner associated with the processor, and each look-up table having a plurality of durations of idle time indexed to corresponding operating conditions; and

a power manager coupled to the processor and the memory, wherein the power manager is configured to;

determine an actual process corner for the processor from the plurality of potential process corners,

determine a first operating condition of the processor,

select a first look-up table from the plurality of look-up tables based on the actual process corner determined for the processor, and

select the duration of idle time for the processor to enter the low power mode from the plurality of durations of idle time in the selected first look-up table based on the first operating condition.

20. The apparatus of claim 19, wherein the power manager is further configured to:

determine the first operating condition of the processor during a first execution of a first application by the processor;

detect a second execution of a second application by the processor;

determine a second operating condition of the processor during the second execution of the second application;

select a second look-up table from the plurality of look-up tables based on a difference between the first operating condition and the second operating condition; and

update the duration of idle time based on the selected second look-up table.