Phase-locked loop circuit

• US 9,160,351 B2
• Filed: 06/30/2014
• Issued: 10/13/2015
• Est. Priority Date: 10/24/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Huan-Neng, Yen, Kuang-Kai, Kuo, Feng-Wei, Lee, Tsung-Hsiung, Jou, Chewn-Pu, Staszewski, Robert Bogdan, Liao, Hsien-Yuan
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/320,168
• Publication Number:
  US 20150116018A1
• Time in Patent Office: 470 Days
• Field of Search: 327147-149, 327156-159
• US Class Current: 1/1
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814

Abstract

A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.

Claims

1. A circuit, comprising:

a digitally-controlled oscillator (DCO) configured for generating an oscillator output signal;

a controller configured for setting an oscillation frequency of the oscillator output signal in accordance with a fractional phase part;

a divider configured for converting the oscillator output signal into N-phased oscillator output signals corresponding to one oscillation period of the digitally-controlled oscillator; and

a phase converter module, comprising;

a period extender, configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator;

a phase finder comprising M*N stages of logic circuits connected in parallel, each stage of the logic circuits configured for sampling the oscillator output signal with one of the M*N-phased oscillator output signals for calculating an estimated value of the fractional phase part; and

a time-to-digital converter configured for sampling one of the N-phased oscillator output signals with a reference-frequency signal to calculate a precise value of the fractional phase part.

2. The circuit of claim 1, wherein the M oscillation period of the digitally-controlled oscillator is divided into M*N sub-periods, the phase finder detects which sub-period the oscillator output signal match, and the time-to-digital converter calculate the precise value of the fractional phase part within one sub-period.

3. The circuit of claim 2, wherein the phase finder is activated when a phase error of the oscillator output signal is larger than one sub-period, and the phase finder is deactivated and the time-to-digital converter is activated when a phase error of the oscillator output signal is less than one sub-period.

4. The circuit of claim 2, wherein the phase converter module further comprises a phase predictor configured for selecting one phase signal from the N-phased oscillator output signals according to a frequency command word (FCW) and providing the selected phase signal to the time-to-digital converter.

5. The circuit of claim 4, wherein the phase predictor comprises:

a phase forwarder configured for predicting which sub-period will the next oscillator output signal match according to the frequency command word (FCW); and

a multiplexer configured for selecting the phase signal from the N-phased oscillator output signals according to the prediction of the phase forwarder.

6. The circuit of claim 1, further comprising:

a counter configured for counting a count value according to the oscillator output signal, and outputting the count value as an integral phase part, wherein the controller is configured to generate a DCO control signal for setting the oscillation frequency in accordance with the integral phase part and the fractional phase part of the oscillator output signal.

7. The circuit of claim 6, wherein the counter is activated to generate the integral phase part when the circuit is initialized and a phase error of the oscillator output signal is larger than one oscillation period of the digitally-controlled oscillator.

8. The circuit of claim 7, wherein the counter is deactivated when the phase error of the oscillator output signal is less than one oscillation period of the digitally-controlled oscillator.

9. The circuit of claim 1, further comprising:

a loop filter disposed between the digitally-controlled oscillator and the controller;

a sigma-delta modulator connected with the loop filter and the digitally-controlled oscillator, configured for synchronizing the digitally-controlled oscillator; and

a reference phase accumulator (RPA) configured for receiving a frequency command word (FCW) and accordingly generating a reference phase signal to the controller.

10. The circuit of claim 1, wherein the circuit is an all-digital phase-locked loop (ADPLL).

11. A circuit, comprising:

a period extender configured for extending an oscillator output signal with N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of a digitally-controlled oscillator, wherein the oscillator output signal is generated by the digitally-controlled oscillator (DCO), the N-phased oscillator output signals are converted from the oscillator output signal by a divider;

a phase finder configured for sampling the M*N-phased oscillator output signals to calculate an estimated value of a fractional phase part utilized for controlling an oscillation frequency of the oscillator output signal, the M oscillation periods of the digitally-controlled oscillator being divided into M*N sub-periods, the phase finder detecting which sub-period the oscillator output signal match; and

a time-to-digital converter configured for one of the N-phased oscillator output signals with a reference-frequency signal to calculate a precise value of the fractional phase part within one sub-period.

12. The circuit of claim 11, wherein the phase finder is activated when a phase error of the oscillator output signal is larger than one sub-period.

13. The circuit of claim 11, wherein the phase finder is deactivated and the time-to-digital converter is activated when a phase error of the oscillator output signal is less than one sub-period.

14. The circuit of claim 11, further comprising a phase predictor configured for selecting one phase signal from the N-phased oscillator output signals according to a frequency command word (FCW), and providing the selected phase signal to the time-to-digital converter.

15. The circuit of claim 14, wherein the phase predictor comprises:

a phase forwarder configured for predicting which sub-period will the next oscillator output signal match according to the frequency command word (FCW); and

a multiplexer configured for selecting the phase signal from the N-phased oscillator output signals according to the prediction of the phase forwarder.

16. A method, comprising:

determining a frequency control word for setting an oscillation frequency of an oscillator output signal;

generating the oscillator output signal by a digitally-controlled oscillator;

converting the oscillator output signal into N-phased oscillator output signals corresponding to one oscillation period of the digitally-controlled oscillator;

extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator;

dividing the M oscillation periods of the digitally-controlled oscillator into M*N sub-periods;

detecting a phase error of the oscillator output signal;

if the phase error is less than one oscillation period of the oscillator output signal and larger than 1/N oscillation period, detecting which sub-period the oscillator output signal matches and calculating an estimated value of a fractional phase part;

if the phase error is less than 1/N oscillation period, calculating a precise value of the fractional phase part within one sub-period; and

tuning the oscillator output signal according to the fractional phase part.

17. The method of claim 16, further comprising:

when the method is initialized, activating a counter for counting an integral phase part according to the oscillator output signal if the phase error is larger than one oscillation period of the oscillator output signal; and

tuning the oscillator output signal according to the integral phase part.

18. The method of claim 17, further comprising:

after the phase error is locked to be less than 1/N oscillation period, turning off the counter configured for counting the integral phase part; and

estimating the integral phase part according to the M*N-phased oscillator output signals corresponding to the M oscillation period of the digitally-controlled oscillator.

19. The method of claim 17, wherein the estimated value of the fractional phase part is calculated by sampling the oscillator output signal with the N-phased oscillator output signals.

20. The method of claim 19, wherein the precise value of the fractional phase part is calculated by sampling one of the N-phased oscillator output signal with a reference-frequency signal.