High speed edge detection

• US 9,160,896 B1
• Filed: 01/25/2013
• Issued: 10/13/2015
• Est. Priority Date: 06/01/2012
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: United States Administrator of National Aeronautics and Space Administration
• Inventors: Prokop, Norman F
• Primary Examiner(s): Tran, Trang U
• Application Number:
  US13/749,773
• Time in Patent Office: 991 Days
• Field of Search: 348/169, 348/333, 348/308, 348/311, 348/143, 348/553, 348/558
• US Class Current: 1/1
• CPC Class Codes: G01N 2021/8896 Circuits specially adapted for system specific signal conditioning
• CPC Class Codes: G01N 21/8851 Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 7/13 Edge detection
• CPC Class Codes: H04N 5/142 Edging; Contouring

Abstract

Analog circuits for detecting edges in pixel arrays are disclosed. A comparator may be configured to receive an all pass signal and a low pass signal for a pixel intensity in an array of pixels. A latch may be configured to receive a counter signal and a latching signal from the comparator. The comparator may be configured to send the latching signal to the latch when the all pass signal is below the low pass signal minus an offset. The latch may be configured to hold a last negative edge location when the latching signal is received from the comparator.

Claims

1. An analog signal detection apparatus, comprising:

a comparator configured to receive an all pass signal and a low pass signal for a pixel intensity in an array of pixels; and

a latch configured to receive a counter signal and a latching signal from the comparator, wherein

the comparator is configured to send the latching signal to the latch when the all pass signal is below the low pass signal minus an offset, and

the latch is configured to hold a last negative edge location when the latching signal is received from the comparator.

2. The analog signal detection apparatus of claim 1, further comprising:

a linear image sensor configured to provide an analog voltage for each pixel in an array of pixels.

3. The analog signal detection apparatus of claim 2, further comprising:

a differentiator configured to convert a clock signal square wave into a short duration pulse; and

a sample and hold component configured to make a continuous image signal from discrete pixel voltages received from the linear image sensor.

4. The analog signal detection apparatus of claim 3, further comprising:

an all pass filter configured to delay the continuous image signal by a constant group delay.

5. The analog signal detection apparatus of claim 1, further comprising:

an offset component configured to determine the offset by subtracting a constant offset voltage from the low pass signal, wherein the offset voltage is configured to provide a predetermined sensitivity to a depth of negative going edges.

6. The analog signal detection apparatus of claim 1, further comprising:

a counter configured to use a clocking signal to determine locations of individual pixels in the array of pixels.

7. The analog signal detection apparatus of claim 1, further comprising:

a second comparator configured to receive the all pass signal and the low pass signal; and

a second latch configured to receive the counter signal and a latching signal from the second comparator, wherein

the second comparator is configured to send the latching signal to the second latch when the all pass signal is above the low pass signal plus the offset, and

the second latch is configured to hold a last positive edge location when the latching signal is received from the second comparator.

8. An analog signal detection apparatus, comprising:

a comparator configured to receive an all pass signal and a low pass signal for a pixel intensity in an array of pixels; and

a latch configured to receive a counter signal and a latching signal from the comparator, wherein

the comparator is configured to send the latching signal to the latch when the all pass signal is above the low pass signal plus an offset,

the latch is configured to hold a last positive edge location when the latching signal is received from the comparator;

a second comparator configured to receive the all pass signal and the low pass signal; and

a second latch configured to receive the counter signal and a latching signal from the second comparator, wherein

the second comparator is configured to send the latching signal to the second latch when the all pass signal is below the low pass signal minus the offset, and

the second latch is configured to hold a last negative edge location when the latching signal is received from the second comparator.

9. The analog signal detection apparatus of claim 8, further comprising:

a linear image sensor configured to provide an analog voltage for each pixel in an array of pixels.

10. The analog signal detection apparatus of claim 9, further comprising:

a differentiator configured to convert a clock signal square wave into a short duration pulse; and

a sample and hold component configured to make a continuous image signal from discrete pixel voltages received from the linear image sensor.

11. The analog signal detection apparatus of claim 10, further comprising:

an all pass filter configured to delay the continuous image signal by a constant group delay.

12. The analog signal detection apparatus of claim 8, further comprising:

an offset component configured to determine the offset by adding a constant offset voltage to the low pass signal, wherein the offset voltage is configured to provide a predetermined sensitivity to a depth of positive going edges.

13. The analog signal detection apparatus of claim 8, further comprising:

a counter configured to use a clocking signal to determine locations of individual pixels in the array of pixels.