Laser assisted transfer welding process

• US 9,161,448 B2
• Filed: 01/18/2012
• Issued: 10/13/2015
• Est. Priority Date: 03/29/2010
• Status: Active Grant

• Current Assignee: Board of Trustees of The University of Illinois, X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: Semprius, Inc.
• Inventors: Menard, Etienne, Meitl, Matthew, Rogers, John A.
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Seven, Evren
• Application Number:
  US13/352,876
• Publication Number:
  US 20120115262A1
• Time in Patent Office: 1,364 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68322 Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/08238 the bonding area connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/24011 : Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24147 : the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/245 : Material
• CPC Class Codes: H01L 2224/24998 : Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/2731 : in liquid form
• CPC Class Codes: H01L 2224/29078 : being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/291 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29101 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29344 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/3012 : Layout
• CPC Class Codes: H01L 2224/32104 : relative to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32146 : the layer connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32227 : the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/75263 : in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/75314 : Auxiliary members on the pressing surface
• CPC Class Codes: H01L 2224/7598 : specially adapted for batch processes
• CPC Class Codes: H01L 2224/76155 : Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/80224 : using a laser
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/82007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/82102 : using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82106 : by subtractive methods
• CPC Class Codes: H01L 2224/83093 : Transient conditions, e.g. gas-flow
• CPC Class Codes: H01L 2224/83121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/83132 : using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83224 : using a laser
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 2224/8384 : Sintering
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/83859 : Localised curing of parts of the layer connector
• CPC Class Codes: H01L 2224/83862 : Heat curing
• CPC Class Codes: H01L 2224/83868 : Infrared [IR] curing
• CPC Class Codes: H01L 2224/83871 : Visible light curing
• CPC Class Codes: H01L 2224/83874 : Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/95001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/9512 : Aligning the plurality of semiconductor or solid-state bodies
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/799 : Apparatus for disconnecting
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/98 : Methods for disconnecting semiconductor or solid-state bodies
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 : the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/043 : Mechanically stacked PV cells
• CPC Class Codes: H01L 31/048 : Encapsulation of modules
• CPC Class Codes: H01L 31/1892 : methods involving the use of temporary, removable substrates
• CPC Class Codes: H01S 5/02315 : Support members, e.g. bases or carriers
• CPC Class Codes: H01S 5/0233 : Mounting configuration of laser chips
• CPC Class Codes: H01S 5/02345 : Wire-bonding
• CPC Class Codes: H01S 5/0235 : Method for mounting laser chips
• CPC Class Codes: H05K 1/18 : Printed circuits structurally associated with non-printed electric components H05K1/0201, H05K1/023, H05K1/0243, and H05K1/16 take precedence
• CPC Class Codes: H05K 13/04 : Mounting of components , e.g. of leadless components
• CPC Class Codes: H05K 13/046 : Surface mounting surface mounted components H05K3/341
• CPC Class Codes: Y02E 10/50 : Photovoltaic [PV] energy
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/51 : Plural diverse manufacturing apparatus including means for metal shaping or assembling

Abstract

A method of printing transferable components includes pressing a stamp including at least one transferable semiconductor component thereon on a target substrate such that the at least one transferable component and a surface of the target substrate contact opposite surfaces of a conductive eutectic layer. During pressing of the stamp on the target substrate, the at least one transferable component is exposed to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer. The stamp is then separated from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate. Related systems and methods are also discussed.

Claims

1. A method of printing transferable components, the method comprising:

providing a eutectic layer comprising a conductive material on a surface of a target substrate;

pressing a stamp including at least one transferable semiconductor component thereon on the target substrate such that the at least one transferable component and the surface of the target substrate contact opposite surfaces of the eutectic layer, wherein the at least one transferable semiconductor component comprises a plurality of semiconductor dies, wherein respective ones thereof are on respective protruding post features of the stamp;

during pressing of the stamp on the target substrate, exposing the at least one transferable component to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer; and

then

separating the stamp from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate.

2. The method of claim 1, wherein the stamp includes a transparent portion at least partially aligned with the at least one transferable component in plan view, and wherein exposing comprises exposing the at least one transferable component to the electromagnetic radiation through the transparent portion of the stamp.

3. The method of claim 2, wherein the electromagnetic radiation comprises laser radiation provided from a light source.

4. The method of claim 3, wherein the laser radiation heats the at least one transferable component, and wherein the at least one transferable component laterally spreads the heat over a surface thereof to reflow the eutectic layer.

5. The method of claim 3, wherein a bandgap of the at least one transferable semiconductor component is transparent to a wavelength of the laser radiation, and wherein the laser radiation heats the eutectic layer to reflow the eutectic layer.

6. The method of claim 1, wherein the surface of the target substrate comprises a rough surface, and wherein the eutectic layer provides a substantially planar interface with the at least one transferable component after the reflow thereof.

7. The method of claim 1, wherein the target substrate comprises an unpolished ceramic substrate, an unpolished polysilicon substrate, an unpolished metal substrate, a printed circuit board, and/or a plastic substrate, and wherein the surface of the target substrate including the eutectic layer thereon is free of an adhesive layer.

8. The method of claim 1, wherein the at least one transferable semiconductor component comprises a plurality of transferable semiconductor components on the stamp, and wherein exposing comprises:

selectively exposing ones of the plurality of transferable components to the electromagnetic radiation through the stamp to reflow portions of the eutectic layer in contact therewith without reflowing other portions of the eutectic layer,

and wherein separating the stamp from the target substrate comprises;

separating the stamp from the target substrate to selectively delaminate the ones of the plurality of transferable components from the stamp without delaminating remaining ones of the plurality of transferable components.

9. The method of claim 8, wherein the plurality of transferable components comprises a continuous array of transferable components, and further comprising the following prior to pressing the stamp on the target substrate:

contacting the stamp with a source substrate including the array of transferable components thereon; and

retracting the stamp from the source substrate to transfer the array of transferable components to the stamp,

wherein the ones of the plurality of transferable components that are delaminated from the stamp comprise a subset of the array.

10. The method of claim 1, further comprising:

patterning the eutectic layer on the target substrate to define a plurality of eutectic patterns thereon prior to pressing the stamp on the target substrate,

wherein the eutectic layer comprises a multi-layer stack including alternating layers of at least two different materials.

11. The method of claim 1, wherein the eutectic layer includes a first eutectic stack adjacent edge portions of the at least one transferable component, and a second eutectic stack between the edge portions, and wherein exposing comprises selectively exposing the edge portions of the at least one transferable component to the electromagnetic radiation to reflow the first eutectic stack without reflowing the second eutectic stack.

12. The method of claim 1, wherein the first eutectic stack comprises a material having a lower eutectic formation temperature than the second eutectic stack,

wherein exposing comprises exposing at least one transferable component to the electromagnetic radiation to reflow the first eutectic stack at a temperature lower than the eutectic formation temperature of the second eutectic stack, and further comprising,

heating the target substrate at a temperature sufficient to selectively reflow the second eutectic stack without reflowing an alloyed material formed upon reflow of the first eutectic stack.

13. The method of claim 12, wherein the second eutectic stack provides an ohmic contact to the at least one transferable component.

14. The method of claim 11, wherein the first eutectic stack comprises a metal alloy, and wherein the second eutectic stack comprises a metal-semiconductor alloy.

15. The method of claim 1, wherein the at least one transferable component comprises a first multi junction solar cell stacked on a second multi junction solar cell having a lower bandgap than the first multi junction solar cell, and wherein an interface between the first and second solar cells includes a eutectic material.

16. The method of claim 15, wherein the interface further includes at least one metal finger protruding from a recess in the second multi junction solar cell, and wherein the at least one metal finger includes the eutectic material thereon.

17. The method of claim 15, further comprising:

an intrinsically doped layer or a P-N diode structure along the interface between the first and second multi-junction solar cells; and

a doped lateral current spreading layer on the intrinsically doped layer or P-N diode structure opposite the second solar cell.

18. The method of claim 1, further comprising:

identifying that the at least one transferable component printed on the target substrate is defective;

contacting the stamp with the at least one transferable component responsive to identifying that the at least one transferable component is defective;

exposing the at least one transferable component to second electromagnetic radiation that is directed through the stamp to reflow the eutectic layer; and

then

retracting the stamp including the at least one transferable component thereon from the target substrate while the eutectic layer is reflowed to delaminate the at least one transferable component from the target substrate.

19. The method of claim 1, wherein the at least one transferable component includes one or more metal finger layers protruding from a surface thereof, and wherein the eutectic layer is on the metal finger layers.

20. The method of claim 1, further comprising:

patterning a metal layer on the target substrate to define a metal interconnect line and a local alignment mark; and

aligning the stamp with the local alignment mark on the target substrate prior to pressing the stamp on the target substrate.

21. The method of claim 1, wherein the at least one transferable component comprises a solar cell, light emitting diode, laser diode, or transistor.

26. The method of claim 1, wherein the stamp is separated from the surface of the target substrate at a delamination rate of greater than 1 millimeter per second, and wherein the eutectic layer comprises a material configured to transition from a liquid phase to a solid phase more quickly than the delamination rate.

27. the method of claim 7, wherein a thickness of the eutectic layer is lower than a peak-to-valley roughness of the target substrate.

22. A process for printing transferable components, comprising the steps of:

(a) providing a eutectic layer comprising a conductive material on a surface of a target substrate;

(b) pressing a stamp including at least one transferable semiconductor component thereon on the target substrate such that the at least one transferable component and the surface of the target substrate contact opposite surfaces of a the eutectic layer, wherein the at least one transferable semiconductor component comprises a plurality of semiconductor dies, wherein respective ones thereof are on respective protruding post features of the stamp;

(c) during pressing of the stamp on the target substrate, exposing the at least one transferable component to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer; and

(d) separating the stamp from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate.

23. The process of claim 22, wherein the stamp includes a transparent portion at least partially aligned with the at least one transferable component in plan view, and wherein the step (c) of exposing comprises:

exposing the at least one transferable component to laser radiation through the transparent portion of the stamp.

24. The process of claim 22, wherein the at least one transferable semiconductor component comprises a plurality of transferable semiconductor components on the stamp, wherein the step (c) of exposing comprises:

selectively exposing ones of the plurality of transferable components to the electromagnetic radiation through the stamp to reflow portions of the eutectic layer in contact therewith without reflowing other portions of the eutectic layer,

and wherein the step (d) of separating the stamp from the target substrate comprises;

separating the stamp from the target substrate to selectively delaminate the ones of the plurality of transferable components from the stamp without delaminating remaining ones of the plurality of transferable components.

25. The process of claim 22, further comprising the steps of:

(e) identifying that the at least one transferable component printed on the target substrate is defective;

(f) contacting the stamp with the at least one transferable component responsive to identifying that the at least one transferable component is defective;

(g) exposing the at least one transferable component to second electromagnetic radiation that is directed through the stamp to reflow the eutectic layer; and

(h) retracting the stamp including the at least one transferable component thereon from the target substrate while the eutectic layer is reflowed to delaminate the at least one transferable component from the target substrate.