Process for manufacturing a membrane microelectromechanical device, and membrane microelectromechanical device

• US 9,162,876 B2
• Filed: 03/13/2012
• Issued: 10/20/2015
• Est. Priority Date: 03/18/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Corona, Pietro, Ferrera, Marco, Varisco, Igor, Campedelli, Roberto
• Primary Examiner(s): Deo, Duy
• Application Number:
  US13/419,230
• Publication Number:
  US 20120237061A1
• Time in Patent Office: 1,316 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/00293 maintaining a controlled atmosphere with processes not provided for in B81C1/00285
• CPC Class Codes: B81C 2201/0116 Thermal treatment for structural rearrangement of substrate atoms, e.g. for making buried cavities
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

Disclosed herein is a microelectromechanical device and a process for manufacturing same. One or more embodiments may include forming a semiconductor structural layer separated from a substrate by a dielectric layer, and opening a plurality of trenches through the structural layer exposing a portion of the dielectric layer. A sacrificial portion of the dielectric layer is selectively removed through the plurality of trenches in membrane regions so as to free a corresponding portion of the structural layer to form a membrane. To close the trenches, the wafer is brought to an annealing temperature for a time interval in such a way as to cause migration of the atoms of the membrane so as to reach a minimum energy configuration.

Claims

1. A process comprising:

forming a microelectromechanical device including;

forming a structural layer on a single dielectric layer on a semiconductor substrate, the structural layer having an inner portion and an outer portion, the dielectric layer having a sacrificial portion and a support portion;

opening a plurality of trenches through the inner portion of the structural layer, the plurality of trenches exposing the sacrificial portion of the dielectric layer;

selectively removing the sacrificial portion of the dielectric layer through the plurality of trenches so as to cause the inner portion of the structural layer to be suspended, thereby forming a membrane the support portion of the dielectric layer remaining between the outer portion of the structural layer and the semiconductor substrate; and

closing the plurality of trenches, the closing the plurality of trenches including exposing the structural layer to an annealing temperature for a time interval.

2. The process according to claim 1, wherein exposing the microelectromechanical device to an annealing temperature for a time interval causes atoms of the membrane to migrate.

3. The process according to claim 1, wherein the annealing temperature is between approximately 1100°

C. and approximately 1250°

C.

4. The process according to claim 1, wherein the time interval has a duration of between approximately 5 minutes and approximately 30 minutes.

5. The process according to claim 1, wherein opening the plurality of trenches includes forming a mask on the structural layer and etching the structural layer using the mask.

6. The process according to claim 5, wherein the mask includes a plurality of apertures.

7. The process according to claim 6, wherein the apertures are uniformly distributed.

8. The process according to claim 6, wherein the apertures are configured so that a ratio of a solid portion of the mask to areas of the apertures is greater than 3:

1.

9. The process according to claim 8, wherein the apertures are configured so that the ratio of the solid portion of the mask to the areas of the apertures is about 8:

1.

10. The process according to claim 6, wherein a distance between adjacent apertures along a direction is greater than a width of the apertures in the same direction.

11. The process according to claim 6, wherein the apertures are arranged on rows and columns along a first direction and a second direction, respectively, and wherein a first distance and a second distance between adjacent apertures respectively along the first direction and the second direction are respectively greater than twice a first width of the apertures in the first direction and greater than twice a second width of the apertures in the second direction.

12. The process according to claim 1, wherein a ratio of an area of the structural layer in a membrane region to areas of cross-sections of each of the plurality of trenches is greater than 3:

1.

13. The process according to claim 12, wherein the ratio of the area of the structural layer in a membrane region to areas of cross-sections of each of the plurality of trenches is about 8:

1.

14. The process according to claim 1, wherein the membrane has a thickness of between 1 μ

m and 3 μ

m.

15. The process according to claim 1, wherein the membrane is made of monocrystalline silicon.

16. A process comprising:

forming a microelectromechanical device including;

forming a structural layer on a dielectric layer on a semiconductor substrate, the structural layer having an inner portion and an outer portion

opening a plurality of trenches through the structural layer, the plurality of trenches exposing a portion of the dielectric layer;

selectively removing a sacrificial portion of the dielectric layer through the plurality of trenches so as to cause a corresponding portion of the structural layer to be suspended, thereby forming a membrane, the membrane being configured to deform in response to a force applied thereto and configured to generate a signal indicative of the deformation; and

closing the plurality of trenches, the closing the plurality of trenches including exposing the structural layer to an annealing temperature for a time interval.

17. The process according to claim 16, wherein exposing the microelectromechanical device to an annealing temperature for a time interval causes atoms of the membrane to migrate.

18. The process according to claim 16, wherein the annealing temperature is between approximately 1100°

C. and approximately 1250°

C.

19. The process according to claim 16, wherein the time interval has a duration of between approximately 5 minutes and approximately 30 minutes.

20. The process according to claim 16, wherein opening the plurality of trenches includes forming a mask on the structural layer and etching the structural layer using the mask.