Techniques for tiling arrays of pixel elements

• US 9,163,995 B2
• Filed: 10/21/2012
• Issued: 10/20/2015
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Santa Barbara Infrared Inc. (Heico Corporation), Indiana Integrated Circuits, LLC, Research Triangle Institute
• Original Assignee: Santa Barbara Infrared Inc. (Heico Corporation), Indiana Integrated Circuits, LLC, Research Triangle Institute
• Inventors: LaVeigne, Joseph Donald, Goodwin, Scott, Lanon, John, Kulick, Jason
• Primary Examiner(s): TANINGCO, MARCUS H
• Application Number:
  US13/656,711
• Publication Number:
  US 20140138543A1
• Time in Patent Office: 1,094 Days
• Field of Search: 250/338.1
• US Class Current: 1/1
• CPC Class Codes: G01J 5/02 Constructional details
• CPC Class Codes: G01J 5/20 using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

Sub-arrays such as tiles or chips having pixel elements arranged on a routing layer or carrier to form a larger array. Through-chip vias or the like to the backside of the chip are used for connecting with the pixel elements. Edge features of the tiles may provide for physical alignment, mechanical attachment and chip-to-chip communication. Edge damage tolerance with minimal loss of function may be achieved by moving unit cell circuitry and the electrically active portions of a pixel element away from the tile edge(s) while leaving the optically active portion closer to the edge(s) if minor damage will not cause a complete failure of the pixel. The pixel elements may be thermal emitter elements for IR image projectors, thermal detector elements for microbolometers, LED-based emitters, or quantum photon detectors such as those found in visible, infrared and ultraviolet FPAs (focal plane arrays), and the like. Various architectures are disclosed.

Claims

1. Method of fabricating and assembling a plurality of tiles having pixel elements to form a large array, wherein the tiles have convex polygonal shapes, wherein each pixel element comprises an electrically active area and optically active area, and unit cell circuitry is associated with each pixel element, wherein the pixel elements are disposed on top of the unit cell circuitry, and wherein and some of the pixel elements are edge pixel elements disposed at the edges of tiles susceptible to damage, comprising:

providing physical alignment features on side edges of the tiles, wherein the physical alignment features on a side edge of a given tile mate with the physical alignment features on a side edge of an adjacent tile in the array; and

further comprising at least one of;

making the unit cell circuitry smaller than the pixel element with which it is associated;

locating the unit cell circuitry for edge pixel elements away from the edges of the tile;

implementing an array of unit cell circuitry with a smaller pitch than the array of pixel elements;

providing routing for a given unit cell circuitry which is located away from its associated the pixel element;

making an electrically active area smaller than the pixel element; and

locating the electrically active areas of edge pixel elements away from the edges of the tile;

and further comprising;

a pixel element disposed at an edge of the tile susceptible to damage is designed to have an edge damage tolerant (EDT) area along at least one edge of the pixel, and the EDT area occupies a fraction of the pixel width by an amount is selected from the group consisting of at least 1%, at least 2%, at least 5%, at least 10%, at least 25%, and the electrically active portion does not extend into the EDT area; and

for pixel elements where the electrically active area is made smaller, maintaining the optically active area as large as possible, including up to the edges of the tile.

2. The method of claim 1, further comprising:

providing back surface connections on the tiles;

mounting the tiles on a routing layer having front surface connections; and

connecting the back surface connections to the front surface connections.

3. The method of claim 2, further comprising at least one of the following features:

mounting the tiles with a sub-pixel size to zero gap at seams between adjacent tiles;

routing substantially all I/O through the back surface connections so that the tiles can be placed edge-to-edge on all sides;

and

providing electrical connection features on side edges of the tiles, wherein the electrical connection features on a side edge of a given tile connect with the electrical connection features on a side edge of an adjacent tile in the array.

4. The method of claim 1, further comprising:

making the unit cell circuitry smaller than the pixel element by an amount selected from the group consisting of at least 1% smaller, at least 2% smaller, at least 5% smaller, at least 10% smaller, at least 20% smaller, at least 30% smaller, at least 40% smaller, and at least 50% smaller than the pixel element with which it is associated.

5. Method of fabricating and assembling a plurality of tiles having pixel elements to form a large array, comprising:

providing back surface connections on the tiles;

mounting the tiles on a routing layer having front surface connections; and

connecting the back surface connections to the front surface connections using through chip routing techniques wherein vias are disposed below the pixel elements;

further comprising;

providing physical alignment features on side edges of the tiles;

wherein the physical alignment features on a side edge of a given tile mate with the physical alignment features on a side edge of an adjacent tile in the array;

wherein the physical alignment features comprise bump features protruding from side edges of the tiles and corresponding recess features extending into side edges of the tiles; and

wherein the tiles have convex polygonal shapes.

6. The method of claim 5, further comprising:

mounting the tiles with a sub-pixel size to zero gap at seams between adjacent tiles.

7. The method of claim 5, further comprising:

routing substantially all I/O through the back surface connections so that the tiles can be placed edge-to-edge on all sides.

8. The method of claim 5, wherein:

the alignment features are located below the front surface of the tile.

9. The method of claim 5, further comprising:

providing electrical connection features on side edges of the tiles;

wherein the electrical connection features on a side edge of a given tile connect with the electrical connection features on a side edge of an adjacent tile in the array and the electrical connections are located below the front surface of the tile.

10. The method of claim 5, wherein each tile comprises:

a first integrated circuit (IC-1) comprising analog portions of pixel elements; and

a second integrated circuit (IC-2) comprising circuitry for the pixel elements;

wherein the pixel elements are thermal radiating or detecting elements.

11. The method of claim 5, wherein each pixel element comprises an electrically active area and optically active area, and unit cell circuitry associated with each pixel element, and some of the pixel elements are edge pixel elements disposed at the edges of tiles susceptible to damage, further comprising at least one of:

making the unit cell circuitry smaller than the pixel element;

locating the unit cell circuitry for edge pixel elements away from the edges of the tile;

implementing an array of unit cell circuitry with a smaller pitch than the array of pixel elements;

providing routing for a given unit cell circuitry which is located away from its associated the pixel element;

making an electrically active area smaller than the pixel element; and

locating the electrically active areas of edge pixel elements away from the edges of the tile.

12. The method of claim 5, wherein each pixel element comprises an electrically active area and an optically active area and unit cell circuitry associated with each pixel element, and some of the pixel elements are edge pixel elements disposed at the edges of tiles susceptible to damage, further comprising making the unit cell circuitry smaller than the pixel element with which it is associated, wherein the unit cell circuitry is smaller than the pixel element by an amount selected from the group consisting of at least 1% smaller, at least 2% smaller, at least 5% smaller, at least 10% smaller, at least 20% smaller, at least 30% smaller, at least 40% smaller, and at least 50% smaller than the pixel element with which it is associated.

13. The method of claim 5, wherein each pixel element comprises an electrically active area and an optically active area and unit cell circuitry associated with each pixel element, and some of the pixel elements are edge pixel elements disposed at the edges of tiles susceptible to damage, wherein:

a pixel element disposed at an edge of the tile susceptible to damage is designed to have an edge damage tolerant (EDT) area along at least one edge of the pixel;

the EDT area occupies a fraction of the pixel width by an amount selected from the group consisting of at least 1%, at least 2%, at least 5%, at least 10%, at least 25%;

the electrically active portion does not extend into the EDT area.

14. The method of claim 5, wherein each pixel element comprises an electrically active area and an optically active area and unit cell circuitry associated with each pixel element, and some of the pixel elements are edge pixel elements disposed at the edges of tiles susceptible to damage, further comprising making the electrically active area smaller than the pixel element wherein for pixel elements where the electrically active area is made smaller, maintaining the optically active area as large as possible, including up to the edges of the tile.

15. An array comprising a plurality of smaller sub-array, each sub-array tile comprising a plurality of pixel elements, characterized by:

a routing layer having front surface connections; and

back surface connections on the tiles for connecting with the front surface connections on the routing layer using through chip routing techniques wherein vias are disposed below the pixel elements; and

physical alignment features on side edges of the tiles, separate from the pixel elements, for ensuring mechanical alignment and registration of the tiles with minimum sub-pixel sized gap therebetween;

wherein the physical alignment features comprise bump features protruding from side edges of the tiles and corresponding recess features extending into side edges of the tiles; and

wherein the tiles have convex polygonal shapes.

16. The array of claim 15, further comprising:

electrical connection features on side edges of the tiles for effecting electrical connections between adjacent tiles.

17. The array of claim 15, wherein:

the tiles are mounted to the routing layer with a sub-pixel size to zero gap at seams between adjacent tiles.

18. The array of claim 15, wherein the pixel elements comprise thermal emitters or detectors.

19. The array of claim 15, wherein:

the pixel elements comprise electrically active areas and unit cell circuitry, and

at least one of the electrically active areas (742, 842, 942) and unit cell circuitry (422, 522, 622) are disposed in selected ones of the pixel elements to be away from edges of the tiles that may sustain edge damage during processing.

20. An array, according to claim 15, wherein the convex polygonal shapes are selected from the group consisting of triangular, square, rectangular, parallelogram, trapezoidal, and hexagonal.