Low-voltage band-gap voltage reference circuit

• US 9,164,527 B2
• Filed: 05/09/2013
• Issued: 10/20/2015
• Est. Priority Date: 05/09/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Huang, Lei
• Primary Examiner(s): PATEL, RAJNIKANT B
• Application Number:
  US13/890,727
• Publication Number:
  US 20130307517A1
• Time in Patent Office: 894 Days
• Field of Search: 327 52- 55, 327/356, 327/359, 327/512, 327/513, 327/539, 323311-316
• US Class Current: 1/1
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

The present application discusses low voltage band-gap voltage reference circuit and methods. In an example the circuit can include a current mirror, an operational amplifier adopting an N-Metal-Oxide-Semiconductor (NMOS) input pair structure, a band-gap output circuit, an adaptive adjustment circuit; and two branches of Bipolar Junction Transistor (BJT). The current mirror can be configured to receive an output signal of the operational amplifier and to provide a current to the two branches of BJT. The operational amplifier can be configured to differentially input voltages at the upper ends of the two branches of BJT, to generate the output signal to the current mirror, and to equalize the voltages at the upper ends of the two branches of BJT using a deep negative feedback.

Claims

1. A low-voltage band-gap voltage reference circuit, comprising:

a current mirror;

an operational amplifier adopting an N-Metal-Oxide-Semiconductor (NMOS) input pair structure;

a bandgap output circuit;

an adaptive adjustment circuit;

two branches of Bipolar Junction Transistor (BJT), and

a resistor network;

wherein the current mirror is configured to receive an output signal of the operational amplifier and to provide a current to the two branches of BJT;

wherein the operational amplifier is configured to differentially input voltages at the upper ends of the two branches of BJT, to generate the output signal to the current mirror, and to equalize the voltages at the upper ends of the two branches of BJT using a deep negative feedback;

wherein the adaptive adjustment circuit is configured to adaptively adjust a base voltage of common base BJTs in the two branches of BJT according to an operating condition of an NMOS input pair in the operational amplifier;

wherein the two branches of BJT are configured to control respective current of the two branches of BJT according to the base voltage of the common base BJTs to ensure normal operation of the operational amplifier;

wherein a first branch of the two branches of BJT include a first resistor,

wherein the resistor network includes;

a second resistor,

a third resistor, and

a fourth resistor,

wherein the second and third resistor are coupled in series between the upper ends of the two branches of BJT,

wherein the fourth resistor is coupled between a first node common to both the second and third resistors and a second node providing the base voltage of the common base BJTs in the two branches of BJT;

wherein the band-gap output circuit is configured to generate an output voltage of the low-voltage band-gap voltage reference circuit by mirroring; and

wherein the output voltage of the low-voltage band-gap voltage reference circuit can be adjusted using a ratio of the first resistor and the fourth resistor.

2. The band-gap voltage reference circuit according to claim 1, wherein the common base BJTs are common base PNPs.

3. The band-gap voltage reference circuit according to claim 2, wherein the operational amplifier adopting the NMOS input pair structure is formed by a first P-Metal-Oxide-Semiconductor (PMOS) transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

wherein the first PMOS transistor and the second PMOS transistor are in cascode connection;

wherein the gate of the first NMOS transistor is connected to the left branch of the two branches of BJT;

wherein the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor;

wherein the source of the first NMOS transistor, configured to serve as a feedback end, is connected to the adaptive adjustment circuit and to the source of the second NMOS transistor;

wherein the gate of the second NMOS transistor is connected to the right branch of the two branches of BJT;

wherein the drain of the second NMOS transistor, configured to serve as an output end, is connected to the current mirror and to the drain of the second PMOS transistor; and

wherein the source of the second NMOS transistor is connected to the source of the first NMOS transistor.

4. The band-gap voltage reference circuit according to claim 3, wherein the current mirror is formed by a third PMOS transistor and a fourth PMOS transistor;

wherein the third PMOS transistor and the fourth PMOS transistor are in cascode connection,

wherein the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the drain of the second NMOS transistor; and

wherein the drains of the third PMOS transistor and the fourth PMOS transistor are connected to the two branches of BJT, respectively.

5. The band-gap voltage reference circuit according to claim 4, wherein the band-gap output circuit is formed by a fifth PMOS transistor and a fifth resistor;

wherein the fifth PMOS transistor is in cascode connection with the first PMOS transistor and the second PMOS transistor; and

wherein the drain of the fifth PMOS transistor is configured to output the output voltage of the band-gap voltage reference circuit and is connected to the fifth resistor.

6. The band-gap voltage reference circuit according to claim 5, wherein the adaptive adjustment circuit is formed by a first adjustment PMOS transistor, a second adjustment PMOS transistor, a third adjustment PMOS transistor, a fourth adjustment PMOS transistor, a fifth adjustment PMOS transistor, a sixth adjustment PMOS transistor and a first adjustment NMOS transistor, a second adjustment NMOS transistor, a third adjustment NMOS transistor, a fifth adjustment NMOS transistor, and a sixth adjustment NMOS transistor,

wherein the first adjustment PMOS transistor, the second adjustment PMOS transistor, and the third adjustment PMOS transistor are in cascode connection;

wherein the source of the fourth adjustment PMOS transistor is connected to the drain of the first adjustment PMOS transistor and to the sources of the fifth adjustment PMOS transistor and the sixth adjustment PMOS transistor;

wherein the drain of the fourth adjustment PMOS transistor is connected to ground via a sixth resistor;

wherein the gate of the fourth adjustment PMOS transistor is connected to a reference voltage;

wherein the gate of the fifth adjustment PMOS transistor is connected to the source of the first adjustment NMOS transistor and the drain of the third adjustment NMOS transistor;

wherein the drain of the fifth adjustment PMOS transistor is connected to the drain of the sixth adjustment PMOS transistor, to the source of the second adjustment NMOS transistor, and to the drain of the sixth adjustment NMOS transistor;

wherein the gate of the sixth adjustment PMOS transistor is connected to the sources of the first NMOS transistor and the second NMOS transistor, and to the drain of the fifth adjustment NMOS transistor;

wherein the sources of the fifth adjustment NMOS transistor and sixth adjustment NMOS transistor are connected to ground,

wherein the gates of the fifth adjustment NMOS transistor and sixth adjustment NMOS transistor are connected to a drive voltage;

wherein the gate of the first adjustment NMOS transistor and the drain of the second adjustment NMOS transistor are connected together; and

wherein the source of the first adjustment NMOS transistor is connected to the base of the common base BJTs in the two branches of BJT.

7. The band-gap voltage reference circuit according to claim 6, wherein at least one of the operational amplifier, the current mirror, the bandgap output circuit or the adaptive adjustment circuit includes a cascode circuit.

8. The band-gap voltage reference circuit according to claim 6, wherein the two branches of BJT is formed by the first resistor, a first BJT and a second BJT;

and

wherein the bases of the first BJT and the second BJT are connected together to the gate of the fifth adjustment PMOS transistor and the source of the first adjustment NMOS transistor, and not to the ground.

9. The band-gap voltage reference circuit according to claim 8, wherein a sum of the currents on the fifth adjustment PMOS transistor and the sixth adjustment PMOS transistor of the adaptive adjustment circuit is equal to the current on the fourth adjustment PMOS transistor;

wherein, when a source voltage of the first NMOS transistor and the second NMOS transistor of the operational amplifier becomes low, the current on the first adjustment NMOS transistor is configured to adjust to a larger value and the base voltage of the common base BJTs in the two branches of BJT is configured to pull up;

wherein, after the base voltage is pulled up, the current in the two branches of BJT is configured to increase and to pull up the source voltage of the first NMOS transistor and the second NMOS transistor of the operational amplifier;

wherein, when the source voltage of the first NMOS transistor and the second NMOS transistor of the operational amplifier becomes high, the current on the first adjustment NMOS transistor is configured to adjust to a smaller value and to pull down the base voltage of the common base BJTs in the two branches of BJT; and

wherein, after the base voltage is pulled down, the current in the two branches of BJT is configured to decrease and to pull down the source voltage of the first NMOS transistor and the second NMOS transistor of the operational amplifier.

10. The band-gap voltage reference circuit according to claim 9, including an offset current source chip configured to detect whether an input voltage is normal and to output an input-voltage-normal signal if the input voltage is normal or an input-voltage-abnormal signal if the input signal is abnormal.

11. The band-gap voltage reference circuit according to claim 10, including an input protecting circuit configured to turn on or off the bandgap voltage reference circuit according to the input-voltage-normal signal or the input-voltage-abnormal signal.

12. The band-gap voltage reference circuit according to claim 11 including an output protecting circuit configured to generate an output-normal signal or an output-abnormal signal according to whether there is the output voltage, and to turn on or off the band-gap voltage reference circuit according to the output-normal signal or the output-abnormal signal.

13. The bandgap voltage reference circuit according to claim 12, including a reference voltage generating circuit configured to provide the adaptive adjustment circuit with the reference voltage.

14. The bandgap voltage reference circuit according to claim 13, including a start-up circuit configured to pull down the output voltage of the operational amplifier during power-on, to start up the operational amplifier rapidly, and to stop pulling down the output voltage of the operational amplifier when there is the output voltage.

15. A method for implementing a low-voltage band-gap voltage reference circuit, the method comprising:

differentially inputting voltages at upper ends of two branches of BJT to an operational amplifier adopting an N-Metal-Oxide-Semiconductor (NMOS) input pair structure, connecting the output of the operational amplifier to a current mirror, and equalizing the voltages at the upper ends of the two branches of BJT using a deep negative feedback;

adaptively adjusting a base voltage of common base BJTs in the two branches of BJT according to an operating condition of an NMOS input pair in the operational amplifier, to control respective current of the two branches of BJT, to ensure normal operation of the operational amplifier;

adjusting a ratio of a first resistor and a fourth resistor to set an output voltage of the low-voltage band-gap voltage reference circuit, wherein a first branch of the two branches of BJT include the first resistor, and wherein a resistor network coupled between the two branches of BJT includes the fourth resistor, the resistor network including;

a second resistor,

a third resistor, and

the fourth resistor,

wherein the second and third resistor are coupled in series between the upper ends of the two branches of BJT,

wherein the fourth resistor is coupled between a first node common to both the second and third resistors and a second node providing the base voltage of the common base BJTs in the two branches of BJT; and

generating the output voltage of the bandgap voltage reference circuit by mirroring.

16. The method according to claim 15, wherein the adaptively adjusting a base voltage of common base BJTs in the two branches of BJT according to an operating condition of an NMOS input pair in the operational amplifier, to control respective current of the two branches of BJT, to ensure normal operation of the operational amplifier includes:

when a source voltage of the NMOS input pair in the operational amplifier becomes low, pulling up the base voltage of the common base BJTs in the two branches of BJT, and pulling up the source voltage of the NMOS input pair of the operational amplifier;

when the source voltage of the NMOS input pair in the operational amplifier becomes high, pulling down the base voltage of the common base BJTs in the two branches of BJT, and pulling down the source voltage of the NMOS input pair of the operational amplifier.

17. The method according to claim 16, wherein the common base BJTs are common base PNPs.

18. The method according to claim 17, including detecting whether an input voltage is normal, and outputting an input-voltage-normal signal or input-voltage-abnormal signal.

19. The method according to claim 18, including turning on or off the bandgap voltage reference circuit according to the input-voltage-normal signal or the input-voltage-abnormal signal.

20. The method according to claim 19, including generating an output-normal signal or an output-abnormal signal according to the fact of whether there is the output voltage, and turning on or off the bandgap voltage reference circuit according to the output-normal signal or the output-abnormal signal.